Abstract: An integrated circuit memory organized in rows and columns of memory cells and having a plurality of redundancy fuses for storing an address of defective rows and columns of the memory cells, in the redundancy fuses, and for selecting a replacement redundant element when an address of a defective row or column is detected. The address code of each defective row or column is recorded in a column of redundancy fuses, each row of the column comprising two cells per digit of the address code, each cell being responsive to either the digit itself or its complement. During a reading of the integrated circuit, only the column that corresponds to the previously recorded address code will not be characterized by a current flow and will be selected as the associated redundant element.