Abstract: Applicant processes to be performed on several processors in a data processing system are synchronized and allocated. The data processing system includes plural processors, each of which derives a control signal indicating that an event has occurred which requires a change in the status of the system, as well as registers for storing signals indicative of a process being executed by the processor. A memory common to the processors is selectively coupled to the processors via a bus. A circuit connected to the memory, the bus and selectively coupled to the processors selectively couples signals between a selected processor and the memory via the bus.

Abstract: Attempts in a data processing system to requisition a process able to have critical section operating phases by means of asynchronous trap(s) are arbitrated. Each time the process enters a critical operating phase, an indicator denoting occupation of a corresponding critical classification is set at one. Each time the process emerges from a critical operating phase the indicator for occupation of the corresponding critical classification is reset to zero. At each asynchronous trap, a trap presence indicator corresponding to the capability of the trap is set to one. Upon arrival of an asynchronous trap, the trap presence indicator corresponding to the capability of the asynchronous trap is set to one. Every time an asynchronous trap is complied with, the asynchronous trap presence indicator corresponding to the fulfilled asynchronous trap is reset to zero.

Abstract: A field selection data operating device consists of three cascade connected circuits: a field selector and shifter circuit, an arithmetical and logical operator circuit and a bit shifter and concatenator circuit. The selector and shifter circuit is controlled by a field length code, a shift value code and a first field bit rank code. It comprises two stages of multiplexing members. The first stage ensures, in circular permutation, a shift of the bytes of an applied data word so as to place the byte containing the bit of the first field bit rank code at the place in the word pointed by the shift value code and the second stage completes the shift to the said bit in the byte and generates an output mask according to the field length code. The mask is also applied to concatenation control inputs of the bit shifter and concatenator circuit.