Abstract: A method of communication between a master unit and a slave unit is of the type including the transmission of messages comprising a useful information word, as well as one or more service bits. The messages include two bits to encode the end-of-transmission information. The value of these bits provides information on the nature of the useful information transmitted to thereby improve the integrity of the communications.

Abstract: A method for communicating between a transmitting unit and a receiving unit over a synchronous serial link. A messages formed by elementary messages is transmitted from the transmitting unit to the receiving unit, with each of the elementary messages including a useful information word. There is established a time gap composed of multiple elementary temporal units after each elementary message is transmitted by the transmitting unit, with the transmitting unit not transmitting during the time gap. During the time gap, an acknowledgement word is received from the receiving unit. The acknowledgement word includes at least one reception bit that is selectively positioned at one of the elementary temporal units of the time gap, and the transmitting unit determines the elementary message that is to be transmitted next based at least partially on at which elementary temporal unit of the time gap the received at least one reception bit is positioned.

Abstract: A method of controlling an electronic circuit is provided. A command is received from a control unit. The command is interpreted in either a first manner if the command is followed by a predetermined dead time, or a second manner if a new command is transmitted before expiration of the predetermined dead time. In a preferred embodiment, the command is interpreted in the second manner only if the new command is identical to the command. Also provided is a chip card that includes an antenna, at least one memory, and a control circuit. When a command is received, the control circuit performs either a first function if the command is followed by a predetermined dead time, or a second function if a new command is transmitted before expiration of the predetermined dead time. Additionally, a telephone apparatus is provided that includes a read/write device for contactless control of a chip card. The read/write device includes an antenna and a control circuit.

Abstract: A method for the identification of electronic cards within an investigation zone includes encoding an identification number on M bits distributed into P blocks of Q bits assigned to each electronic card. Reconstruction of the block-by-block identification numbers is performed according to a tree-like iterative algorithm. In this iterative algorithm, each iteration includes a step for transmitting an interrogation message intended for certain electronic cards. Each iteration also includes a step for transmitting, by each of the electronic cards, a response message having a service bit in a narrow time window whose positioning in a sequence of 2Q successive identical windows indicates the value of an as yet unidentified block of bits of its identification number.

Abstract: A method for communicating between a transmitting unit and a receiving unit. A messages formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device, means for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device.

Abstract: A method for communicating between a transmitting unit and a receiving unit. A message formed by elementary messages is transmitted from the transmitting unit to the receiving unit, and at least one reception bit is transmitted from the receiving unit to the transmitting unit. The reception bit (or bits) allows the transmitting unit to determine the elementary message that is to be transmitted next. In a preferred method, at least two reception bits are transmitted from the receiving unit and the values of the reception bits indicate the elementary message that is to be transmitted next by the transmitting unit. The present invention also provides a receiving device for receiving messages from a transmitting device. The receiving device includes an interface for receiving a transmitted message from the transmitting device and for analyzing a received elementary message to determine if it was properly received, and a transmitter for transmitting at least one reception bit to the transmitting device.

Abstract: A method for the control of an electronic circuit of the type includes at least one access pin to receive and/or deliver control signals, includes the generation, in a control unit, of control signals from data elements received serially through a data transfer input/output device. The method also includes the following steps: (1) extracting a control word included in the data received serially; and (2) decoding the control word extracted in the previous step in order to perform an operation, as a function of the value of the control word, thus modifying the logic state of at least one control signal.

Abstract: A method is provided for identifying electronic cards. According to the method, an interrogation message is sent to the electronic cards, and at least two different types of markers are sent to the electronic cards. The markers of the first type determine the time slots in the sequence, and the markers of the second type cause the electronic cards to change to predetermined states. In a preferred method, the identification method is interrupted when a marker of the second type is sent. Also provided is a method of identifying electronic cards by receiving an interrogation message from an interrogation unit, and at least two different types of markers are received from the interrogation unit. The markers of the first type determine the time slots in the sequence, and the markers of the second type cause the electronic cards to change to predetermined states. Additionally, communication systems of the type in which an interrogation unit identifies electronic cards are provided.

Abstract: A method for the identification of electronic cards within an investigation zone includes an identification number uniquely assigned to each electronic card. The method reconstructs the identification numbers according to a tree-like iterative algorithm. The algorithm includes the steps of sending an interrogation message intended for certain electronic cards present, and steps for sending a response message by the electronic cards. The response message includes a variable number whose value depends on the identification number of the electronic card. The interpretation of the existence and of the position at which a collision occurs between the bits of the variable numbers received enables the gradual reconstruction, possibly by blocks of bits, of the as yet unidentified bits of an identification number of an electronic card present.

Abstract: Disclosed is a method and a device to improve the data output speed of a memory associated with a central processing unit of a microcomputer, should the reading be done at consecutive addresses of the memory in the mode known as the “burst read” mode. The address register is of the type with incrementation controlled by a sequencing circuit. The read register is followed by a data register which records the contents of the read register so as to free this read register to record the contents of the memory cells that are selected by the incremented address.

Abstract: An apparatus and method for reading of a memory associated with a central processing unit that does not permit a fraudulent individual to discover the addressing codes of the memory corresponding to the performance of a particular wherein the successive codes for the addressing of the memory are deduced from one another according to a function of prediction defined by the programmer. These addressing codes are verified by the addressing circuits of the memory by means of a computation and comparison procedure that know the prediction function.

Abstract: An output buffer circuit for logic signals produces an output logic signal from an input logic signal. It comprises a storage circuit capable of storing the logic state of the input signal and an output stage to produce the output signal as a function of the logic state stored in the storage circuit. A control circuit comprises a circuit for the comparison of the input and output signals. The control circuit produces an updating command signal whose logic state represents the relationship existing between the logic states of the input and output signals. This updating signal activates the storage, in the storage circuit, of the state of the input signal.

Abstract: The invention relates to memories associated with the central processing units of microcomputers and more particularly, in such memories, to an architecture and device used to protect certain zones of the memory against unauthorized reading operations. The zones of the memory to which access must be authorized to fulfill certain functions are listed by codes recorded in a first memory. Access to these zones is authorized only if the central processing unit gives corresponding codes through a second memory whose contents are compared with those of the first memory. The invention can be applied to microcomputers and microcontrollers, especially those used in mobile telephone sets.

Abstract: The circuit is for the measurement of the current of the memory cells of an electrically modifiable non-volatile memory. The read circuit is complemented by two current sources to improve the biasing of the current mirror of the read circuit during the measurement.

Abstract: In order to carry out the automatic selection of redundant memory elements (rows or columns) to replace defective elements, the addresses of the elements to be replaced are compared with the current address. In order to improve the reliability by reducing the number of non-volatile memory cells normally containing the addresses of the elements to be replaced, the selection circuit has means to compute certain of these addresses from an actually stored address. Application notably to FLASH EEPROMs.

Abstract: Electrically programmable memories, in particular EPROMs, generally have an internal signature which can be read by the memory-programming device. This internal signature indicates the origin of the part (manufacturer's identification) and the appropriate programming mode for the part (fast programming, "intelligent" programming, etc.). Here, it is proposed that this information be recorded in a UPROM (unerasable programmable read-only) memory, i.e., in practice an EPROM memory masked by a layer of aluminium which prevents its erasure by ultraviolet rays.

Abstract: The integrated circuit memory has a matrix of cells and a plurality of circuits enabling the selective application, to the cells, of programming and erasure potentials. These circuits are controlled by an integrated state machine programmed to perform algorithms adapted to the operations to be performed. In order to facilitate the devising and perfecting of these algorithms, the memory includes selection means enabling an external tester to be substituted for the state machine. A particularly advantageous application is in "FLASH EEPROM" memories.

Abstract: In reading circuits for memories in integrated circuit form, notably non-volatile memories, a differential amplifier for reading the memory cell is connected to a precharged bit line and a reference line. A balancing device balances the potentials of the bit line and reference line, and the corresponding inputs to the differential amplifier, before the reading phase of the circuit. The balancing device includes a follower amplifier having an input connected to the differential amplifier and an output connected to the bit line to inject a load current to the bit line during a balancing phase of the reading circuit.

Abstract: A method for erasing a non-volatile electrically erasable and programmable integrated circuit memory that is divided into N sectors selected separately by addressing circuits and the cells for each sector being selected by row and column addressing circuits wherein an erasure pulse is applied simultaneously to all the sectors. The checking of the erasure of each sector leads to the locking of the sector when no defect is detected. A new erasure pulse is applied only to the unlocked sectors and only the unlocked sectors are rechecked. Also, a circuit for locking sectors in order to implement the method is disclosed.

Abstract: In reading circuits for memories in integrated circuit form, notably non-volatile memories, to obtain a better compromise between reading speed and the reliability of the information read, there is proposed a reading circuit. A differential amplifier for reading a memory cell is connected to a precharged bit line and reference line. A follower amplifier balances the input potentials of the differential amplifier before the reading phase. The follower amplifier has one input connected to the output of the differential amplifier and is connected during the balancing phase in such a way that it injects a load current to the- bit line in a direction tending to cancel the output voltage of the differential amplifier. A cascode transistor can be used to accelerate the reading.