Abstract: The invention relates to a method for producing a support for the production of a semiconductor structure based on group III nitrides, characterised in that the method comprises the steps of: formation (100) of a buffer layer (20) on a substrate (10), said buffer layer comprising an upper surface layer based on group III nitrides, and deposition (200) of a crystalline layer (30) on the buffer layer, said crystalline layer being deposited from silicon atoms so as to cover the entire surface of the upper layer based on group III nitrides. The invention also relates to a support obtained by the method, to a semiconductor structure based on the support, and to the method for the production thereof.

Abstract: The invention relates to a method for producing a semiconductor structure, characterized in that the method comprises a step (201) of depositing a crystalline passivation layer continuously covering the entire surface of a layer based on group III nitrides, said crystalline passivation layer, which is deposited from a precursor containing silicon atoms and a flow of nitrogen atoms, consisting of silicon atoms bound to the surface of the layer based on group III nitrides and arranged in a periodical arrangement such that a diffraction image of said crystalline passivation layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises: two fractional order diffraction lines (0, ??) and (0, ??) between the central line (0, 0) and the integer order line (0, ?1), and two fractional order diffraction lines (0, ?) and (0, ?) between the central line (0, 0) and the integer order line (0, 1).

Abstract: The invention relates to a method for producing a support for the production of a semiconductor structure based on group III nitrides, characterised in that the method comprises the steps of: formation (100) of a buffer layer (20) on a substrate (10), said buffer layer comprising an upper surface layer based on group III nitrides, and deposition (200) of a crystalline layer (30) on the buffer layer, said crystalline layer being deposited from silicon atoms so as to cover the entire surface of the upper layer based on group III nitrides. The invention also relates to a support obtained by the method, to a semiconductor structure based on the support, and to the method for the production thereof.

Abstract: The invention relates to a method for producing a semiconductor structure, characterised in that the method comprises a step (201) of depositing a crystalline passivation layer continuously covering the entire surface of a layer based on group III nitrides, said crystalline passivation layer, which is deposited from a precursor containing silicon atoms and a flow of nitrogen atoms, consisting of silicon atoms bound to the surface of the layer based on group III nitrides and arranged in a periodical arrangement such that a diffraction image of said crystalline passivation layer obtained by grazing-incidence diffraction of electrons in the direction [1-100] comprises: two fractional order diffraction lines (0, ??) and (0, ??) between the central line (0, 0) and the integer order line (0, ?1), and two fractional order diffraction lines (0, ?) and (0, ?) between the central line (0, 0) and the integer order line (0, 1).

Abstract: A Light-emitting device comprises a monolithic matrix of III-nitride elements, the matrix comprising at least one first stack of quantum wells or of planes of quantum dots able to emit photons at at least one second wavelength by optical pumping by the photons emitted by the first stack, and a region separating the two stacks, and first and second electrodes arranged to allow an electrical current to pass through the stacks, the second stack is n-doped, the separating region comprises a tunnel junction having an n++-doped region arranged on the same side as the second stack and a p++-doped region arranged on the opposite side and the first stack is arranged between separating region and at least one n-doped layer. Method for manufacturing such device.

Abstract: The disclosure relates to a making a matrix of III-V nitride, the matrix including at least an active first portion through which an electrical current passes and at least a passive second portion through which no electrical current passes, the matrix including at least a first zone forming a first quantum confinement region made of a III-V nitride, the first zone being positioned in the active first portion, and at least a second zone forming a second quantum confinement region made of III-V nitride, such that the second zone is positioned to the passive portion of the matrix.

Abstract: The disclosure relates to a making a matrix of III-V nitride, the matrix including at least an active first portion through which an electrical current passes and at least a passive second portion through which no electrical current passes, the matrix including at least a first zone forming a first quantum confinement region made of a III-V nitride, the first zone being positioned in the active first portion, and at least a second zone forming a second quantum confinement region made of III-V nitride, such that the second zone is positioned to the passive portion of the matrix.

Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.

Abstract: The invention relates to a device comprising a matrix made of III-V nitride, said matrix comprising at least an active first portion through which an electrical current passes and at least a passive second portion through which no electrical current passes, said matrix comprising at least a first zone forming a first quantum confinement region made of a III-V nitride, said first zone being positioned in said active first portion, and at least a second zone forming a second quantum confinement region made of III-V nitride, characterized in that said second zone is positioned to said passive portion of said matrix.

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: A process is provided for integrating a III-N component, such as GaN, on a (001) or (100) nominal silicon substrate. There are arranged a texture of elementary areas each comprising an individual surface, with the texture comprising at least one hosting area intended to receive a III-N component. A mask layer is deposited on non-hosting areas which are not intended to receive a III-N type component. The hosting area is locally prepared so as to generate on the surface of the area one domain comprising one single type of terrace. There is grown by Molecular Beam Epitaxy or Metalorganic Vapor Phase Epitaxy on the hosting area one intermediary AlN buffer layer, followed by the growth of one III-N based material so as to realize a substantially monocrystalline structure. There is eliminated the mask layer located on non-hosting areas as well as surface polycrystalline layers deposited above the mask layers, and MOS/CMOS structures are subsequent integrated on at least some of the non-hosting areas.

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: The invention concerns a monocrystalline coating crack-free coating of gallium nitride or mixed gallium nitride and another metal, on a substrate likely to cause extensive stresses in the coating, said substrate being coated with a buffer layer, wherein: at least a monocrystalline layer of a material having a thickness ranging between 100 and 300 nm, preferably between 200 and 250 nm, and whereof crystal lattice parameter is less than the crystal lattice parameter of the gallium nitride or of the mixed gallium nitride with another metal, is inserted in the coating of gallium nitride or mixed gallium nitride with another metal. The invention also concerns the method for preparing said coating. The invention further concerns electronic and optoelectronic devices comprising said coating.

Abstract: A device includes a silicon substrate provided with a coating including at least one stacking constituted by a plane of GaN or GaInN quantum dots emitting visible light at room temperature in a respective layer of AIN or GaN. The method of making the device is also disclosed. The device can be incorporated in electroluminescent devices and exchange devices, emitting white light in particular.

Abstract: An electromagnetic wave detector formed of semiconductor materials includes at least one quantum well in which there is provided a fine layer of a material with a gap width that is smaller than that of the quantum well layer. For example, in the case of a GaAlAs/GaAs/GaAlAs, there is provision for a fine layer of InAs. In this way, the difference of energy levels between the two permitted levels is increased and detection of short wavelengths may be accomplished.

Abstract: A process for producing a "metal to compound semiconductor" contact having a potential barrier of predetermined height. By this is meant a Schottky contact or an ohmic contact. The process comprises, before deposition of the metal, perfectly cleaning the semiconductor so as to remove in particular oxygen, then depositing sulphur or selenium on its surface by the action of hydrogen sulphide or hydrogen selenide, and, after deposition of the metal, effecting a heat treatment of the contact. In this way, an ohmic contact is obtained. The Schottky contact is obtained by the action of hydrogen sulphide or hydrogen selenide and then pure oxygen at very low pressure.

Abstract: A system for automatic regulation of the density of a given molecular type at a pre-arranged point in an apparatus called a "flux or molecular jet", intended to make epitaxy layers. In a vacuum enclosure a probe for mass spectrometry analysis (electrostatic, four pole apparatus) picks up the types projected by evaporating units, ionizes them, filters and detects them as a function of their respective masses. The heating in each unit is regulated by a servo-control loop which contains means for analyzing the type concerned.