Abstract: The converter comprises a memory (SRAM) having first and second ports, a first port management circuit (SPM) connected to the first port, to an incoming synchronous multiplex line (ME) and to an outgoing synchronous multiples line (MS), and a second port management circuit (APM) connected to the second port, to an incoming asynchronous link (LE) via an FIFO type packet memory (M) and to an outgoing asynchronous link (LS). An external command (MF) applied to the port management circuits selects the converter operating mode; in a first mode (M32) each time slot of a frame of a synchronous multiplexed signal is assigned to one communication channel and in a second mode (M1) all the time slots of a synchronous frame are assigned to one channel.

Abstract: A bridge for connecting an IEEE 802.3 local area network to an asynchronous time-division multiplex telecommunication network comprises a part implementing the functions of layer 2.1 of an asynchronous time-division multiplex telecommunication network transmission protocol and a part which is a conventional local area network interface implementing the functions of layer 1 of the local area network data transmission protocol. The circuit is applicable to the transmission of data between different local area networks.

Abstract: The apparatus comprises a protocol processor circuit connected to a network, a memory having a transmit memory and a receive memory, a transmit control memory and a receive control memory. The memories are connected to the processor circuit via a data bus and to a level 2.2 processor by a bus. The control memories are of the FIFO type, with the transmit control memory being written to by the high level 2.2 processor and being read from by the processor circuit, and with the receive control memory being written to by the processor circuit and read from by the level 2.2 processor. The processor circuit transmits and receives cells containing signalling information, and it performs level 2.1 function of the protocol: detecting transmission errors on a cell-by-cell basis, detecting loss for added cells, splitting up a message delivered by the level 2.2 processor into cells, and de-interlacing cells relating to a plurality of messages on reception.

Abstract: The method consists in using a sawtooth signal at the output from a lowpass filter of a phase lock loop, in multiplying it by a low frequency squarewave signal, in integrating the resulting multiplied signal in order to obtain a sweep signal, and in controlling a voltage controlled oscillator of the phase lock loop by means of the sweep signal. The apparatus comprises a multiplier (7) and a low frequency generator (8). It may also include, prior to the multiplier, a hysteresis comparator (5) and a highpass filter (6). The output (S7) of the multiplier (7) is connected to a loop filter (3) in said phase lock loop in order to integrate the multiplied signal.