Patents by Inventor Jean-Michel Guillot

Jean-Michel Guillot has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8049271
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Grant
    Filed: May 3, 2010
    Date of Patent: November 1, 2011
    Assignee: Vishay General Semiconductor LLC
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Publication number: 20100207198
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Application
    Filed: May 3, 2010
    Publication date: August 19, 2010
    Applicant: GS GENERAL SEMICONDUCTOR LLC
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 7736976
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Grant
    Filed: December 4, 2007
    Date of Patent: June 15, 2010
    Assignee: Vishay General Semiconductor LLC
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Publication number: 20080142880
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a second conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Application
    Filed: December 4, 2007
    Publication date: June 19, 2008
    Applicant: Vishay General Semiconductor LLC
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 7304347
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Grant
    Filed: November 13, 2003
    Date of Patent: December 4, 2007
    Assignee: Vishay General Semiconductor Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Publication number: 20040097028
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Application
    Filed: November 13, 2003
    Publication date: May 20, 2004
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Publication number: 20040075160
    Abstract: A semiconductor device includes a heavily doped first layer of a first conductivity type having a bulk portion and a mesa portion disposed above the bulk portion. A second layer of a second conductivity type is deposited on the mesa portion of the first layer to form a p-n junction therewith. The second layer is more lightly doped than the first layer. A contact layer of the second conductivity type is formed on the second layer. First and second electrodes electrically contact the bulk portion of the first layer and the contact layer, respectively.
    Type: Application
    Filed: October 18, 2002
    Publication date: April 22, 2004
    Inventors: Jack Eng, John Naughton, Lawrence Laterza, James Hayes, Jean-Michel Guillot
  • Patent number: 6649477
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: November 18, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 6624494
    Abstract: A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region.
    Type: Grant
    Filed: October 4, 2002
    Date of Patent: September 23, 2003
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Publication number: 20030068863
    Abstract: A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region.
    Type: Application
    Filed: October 4, 2002
    Publication date: April 10, 2003
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Publication number: 20030068854
    Abstract: A method is provided for forming a power semiconductor device. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one terraced trench in the epitaxial layer. The terraced trench has a plurality of portions that differ in width to define at least one annular ledge therebetween. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material lining the annular ledge and said trench bottom and into adjacent portions of the epitaxial layer. The dopant is diffused to form at least one annular doped region in the epitaxial layer and at least one other region located below the annular doped region.
    Type: Application
    Filed: October 4, 2001
    Publication date: April 10, 2003
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 6465304
    Abstract: A power semiconductor device and a method of forming the same is provided. The method begins by providing a substrate of a first conductivity type and then forming a voltage sustaining region on the substrate. The voltage sustaining region is formed by depositing an epitaxial layer of a first conductivity type on the substrate and forming at least one trench in the epitaxial layer. A barrier material is deposited along the walls of the trench. A dopant of a second conductivity type is implanted through the barrier material into a portion of the epitaxial layer adjacent to and beneath the bottom of the trench. The dopant is diffused to form a first doped layer in the epitaxial layer and the barrier material is removed from at least the bottom of the trench. The trench is etched through the first doped layer and a filler material is deposited in the trench to substantially fill the trench, thus completing the voltage sustaining region.
    Type: Grant
    Filed: October 4, 2001
    Date of Patent: October 15, 2002
    Assignee: General Semiconductor, Inc.
    Inventors: Richard A. Blanchard, Jean-Michel Guillot
  • Patent number: 5677562
    Abstract: A semiconductor device, which has a silicon body that includes at least one planar p-n junction that intersects a surface of the body, uses a multilayer arrangement that includes a first layer of thermally grown silicon dioxide, a second layer of Chemical-Vapor-Deposited (CVD) silicon nitride, a third layer of CVD oxygen-rich polysilicon, and a fourth layer of CVD silicon dioxide to passivate the junction. Common metallization contacts both the diffused region of the planar junction and the oxygen-rich polysilicon.
    Type: Grant
    Filed: May 14, 1996
    Date of Patent: October 14, 1997
    Assignee: General Instrument Corporation of Delaware
    Inventors: Michael L. Korwin-Pawlowski, Jean-Michel Guillot, James J. Brogle
  • Patent number: 5610434
    Abstract: Mesa diodes of improved mechanical properties are formed by providing a central depression in the regions of the chip from which the mesa is formed before the diffusion step that forms the rectifying junction in the mesa. In symmetric diodes, symmetric depressions are formed on both the top and bottom surfaces of the chip.
    Type: Grant
    Filed: November 7, 1995
    Date of Patent: March 11, 1997
    Assignee: General Instrument Corporation of Delaware
    Inventors: James J. Brogle, Harold P. Davis, Jean-Michel Guillot, Michael Korwin-Pawlowski
  • Patent number: D659476
    Type: Grant
    Filed: January 31, 2011
    Date of Patent: May 15, 2012
    Assignee: Compagnie des Arts de la Table
    Inventor: Jean-Michel Guillot