Patents by Inventor Jean-Michel Hartmann

Jean-Michel Hartmann has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210066535
    Abstract: A method of forming an opening in an insulating layer covering a semiconductor region including germanium, successively including: the forming of a first masking layer on the insulating layer; the forming on the first masking layer of a second masking layer including an opening; the etching of an opening in the first masking layer, in line with the opening of the second masking layer; the removal of the second masking layer by oxygen-based etching; and the forming of the opening of said insulating layer in line with the opening of the first masking layer, by fluorine-based etching.
    Type: Application
    Filed: August 27, 2020
    Publication date: March 4, 2021
    Applicant: Commissariat à l'Énergie Atomique et aux Énergies Alternatives
    Inventors: Willy Ludurczak, Abdelkader Aliane, Jean-Michel Hartmann, Zouhir Mehrez, Philippe Rodriguez
  • Publication number: 20200313008
    Abstract: A method of forming an area of electric contact with a semiconductor region mainly made of germanium, comprising the forming of a first area made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms. There is also described a device including such a contacting area.
    Type: Application
    Filed: March 26, 2020
    Publication date: October 1, 2020
    Applicant: Commissariat à I'Énergie Atomique et aux Énergies Alternatives
    Inventors: Willy Ludurczak, Philippe Rodriguez, Jean-Michel Hartmann, Abdelkader Aliane, Zouhir Mehrez
  • Patent number: 10699902
    Abstract: The invention pertains to a process for producing a strained layer based on germanium-tin (GeSn). The process includes a step of producing a semiconductor stack containing a layer based on GeSn and having an initial strain value that is non-zero; a step of structuring the semiconductor stack so as to form a structured portion and a peripheral portion, the structured portion including a central section linked to the peripheral portion by at least two lateral sections having an average width greater than an average width of the central section; and a step of suspending the structured portion, the central section then having a final strain value higher than the initial value.
    Type: Grant
    Filed: August 23, 2017
    Date of Patent: June 30, 2020
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent Reboud, Jean-Michel Hartmann, Alexei Tchelnokov, Vincent Calvo
  • Publication number: 20200194259
    Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.
    Type: Application
    Filed: December 17, 2019
    Publication date: June 18, 2020
    Applicants: COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES, UNIVERSITÉ GRENOBLE ALPES, CENTRE NATIONAL DE LA RECHERCHE SCIENTIFIQUE
    Inventors: Pierre-Edouard RAYNAL, Pascal BESSON, Jean-Michel HARTMANN, Virginie LOUP, Laurent VALLIER
  • Publication number: 20200176503
    Abstract: A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.
    Type: Application
    Filed: November 26, 2019
    Publication date: June 4, 2020
    Applicant: Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Louis OUVRIER-BUFFET, Abdelkader ALIANE, Jean-Michel HARTMANN, Julie WIDIEZ
  • Publication number: 20190244813
    Abstract: The invention pertains to a process for producing a strained layer based on germanium-tin (GeSn). The process includes a step of producing a semiconductor stack containing a layer based on GeSn and having an initial strain value that is non-zero; a step of structuring the semiconductor stack so as to form a structured portion and a peripheral portion, the structured portion including a central section linked to the peripheral portion by at least two lateral sections having an average width greater than an average width of the central section; and a step of suspending the structured portion, the central section then having a final strain value higher than the initial value.
    Type: Application
    Filed: August 23, 2017
    Publication date: August 8, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Vincent REBOUD, Jean-Michel HARTMANN, Alexei TCHELNOKOV, Vincent CALVO
  • Patent number: 10354870
    Abstract: First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.
    Type: Grant
    Filed: November 5, 2015
    Date of Patent: July 16, 2019
    Assignee: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yann Bogumilowicz, Jean-Michel Hartmann
  • Publication number: 20190177836
    Abstract: A method for producing a waveguide including a germanium-based core and a cladding is provided, the method including a step of “low temperature” depositing of a shell after forming the core by engraving, such that the deposition temperature is less than 780° C., followed by a step of “high temperature” depositing of a thick encapsulation layer. The shell and the encapsulation layer at least partially form the cladding of the waveguide. Optionally, a step of annealing under hydrogen at a “low temperature”, less than 750° C., precedes the deposition of the shell. These “low temperature” annealing and depositing steps advantageously make it possible to avoid a post-engraving alteration of the free surfaces of the core during the forming of the cladding which is less germanium-rich.
    Type: Application
    Filed: December 7, 2018
    Publication date: June 13, 2019
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Michel Hartmann, Mickael Brun, Jean-Marc Fedeli, Maryse Fournier
  • Publication number: 20180261454
    Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.
    Type: Application
    Filed: June 27, 2016
    Publication date: September 13, 2018
    Inventors: Xinyu BAO, Zhiyuan YE, Jean-Baptiste PIN, Errol SANCHEZ, Franck BASSANI, Thierry BARON, Yann BOGUMILOWICZ, Jean-Michel HARTMANN
  • Publication number: 20170004968
    Abstract: A semiconductor device is disclosed that has a semiconductor substrate having a crystal structure with a <1,0,0> plane and a <1,1,0> plane and a surface that forms an angle of about 0.3 degrees to about 0.7 degrees with the <1,0,0> plane in the direction of the <1,1,0> plane; and a compound semiconductor layer formed on the semiconductor substrate. The compound semiconductor layer is free of antiphase boundaries, and has a thickness between about 200 nm and about 1,000 nm.
    Type: Application
    Filed: June 27, 2016
    Publication date: January 5, 2017
    Inventors: Xinyu BAO, Zhiyuan YE, Jean-Baptiste PIN, Errol SANCHEZ, Franck BASSANI, Thierry BARON, Yann BOGUMILOWICZ, Jean-Michel HARTMANN
  • Patent number: 9460923
    Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.
    Type: Grant
    Filed: March 20, 2014
    Date of Patent: October 4, 2016
    Assignees: STMicroelectronics (Crolles 2) SAS, Commisariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Aomar Halimaoui, Jean-Michel Hartmann
  • Patent number: 9379213
    Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
    Type: Grant
    Filed: August 4, 2014
    Date of Patent: June 28, 2016
    Assignees: Commissariat a l'energie atomique et aux energies alternatives, STMICROELECTRONICS SA
    Inventors: Perrine Batude, Jean-Michel Hartmann, Benoit Sklenard, Maud Vinet
  • Publication number: 20160126095
    Abstract: First, second and third series of samples are successively made so as to determine the influence of the deposition parameters on the crystallographic quality of a layer of semiconductor material of III-V type. The parameters studied are successively the deposition pressure, the deposition temperature and the deposited thickness of a sub-layer of semiconductor material of III-V type so as to respectively determine a first deposition pressure, a first deposition temperature at the first deposition pressure, and a first deposited thickness at the first deposition temperature and at the first deposition pressure. The sub-layer of semiconductor material of III-V type is thickened by ways of a second layer of semiconductor material of III-V type deposited under different conditions.
    Type: Application
    Filed: November 5, 2015
    Publication date: May 5, 2016
    Applicant: COMMISSARIAT À L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Yann BOGUMILOWICZ, Jean-Michel HARTMANN
  • Patent number: 9246045
    Abstract: Fabrication of a photodetector is performed on a substrate comprising a first portion successively provided with a first semiconductor film, an electrically insulating layer, a second semiconductor film, and a protection layer. The substrate also comprises a second portion not comprising the second semiconductor film. It further comprises a third portion not comprising the second semiconductor film and the protection layer. The second semiconductor film is etched in the first portion to form a cavity. A PIN/NIP diode is formed in the third portion at least by means of deposition of a third semiconductor material which also comes and fills the cavity. A conversion layer is deposited to absorb a light signal originating from the second semiconductor film and to convert the light signal into an electric signal, the conversion layer electrically connecting the PIN/NIP diode.
    Type: Grant
    Filed: December 15, 2014
    Date of Patent: January 26, 2016
    Assignee: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventors: Jean-Michel Hartmann, Yann Bogumilowicz, Jean-Marc Fedeli
  • Publication number: 20150171259
    Abstract: Fabrication of a photodetector is performed on a substrate comprising a first portion successively provided with a first semiconductor film, an electrically insulating layer, a second semiconductor film, and a protection layer. The substrate also comprises a second portion not comprising the second semiconductor film. It further comprises a third portion not comprising the second semiconductor film and the protection layer. The second semiconductor film is etched in the first portion to form a cavity. A PIN/NIP diode is formed in the third portion at least by means of deposition of a third semiconductor material which also comes and fills the cavity. A conversion layer is deposited to absorb a light signal originating from the second semiconductor film and to convert the light signal into an electric signal, the conversion layer electrically connecting the PIN/NIP diode.
    Type: Application
    Filed: December 15, 2014
    Publication date: June 18, 2015
    Inventors: Jean-Michel HARTMANN, Yann BOGUMILOWICZ, Jean-Marc FEDELI
  • Publication number: 20150044841
    Abstract: Method for fabricating a transistor comprising the steps consisting of: forming sacrificial zones in a semi-conductor layer, either side of a transistor channel zone, forming insulating spacers on said sacrificial zones against the sides of the gate of said transistor, removing said sacrificial zones so as to form cavities, with the cavities extending on either side of said channel zone and penetrating under said spacers, forming doped semi-conductor material in said cavities, with said semi-conductor material penetrating under said spacers.
    Type: Application
    Filed: August 4, 2014
    Publication date: February 12, 2015
    Applicants: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENE ALT, STMICROELECTRONICS SA
    Inventors: Perrine BATUDE, Jean-Michel HARTMANN, Benoit SKLENARD, Maud VINET
  • Publication number: 20140284769
    Abstract: The present disclosure concerns a method involving: forming a strained silicon germanium layer by epitaxial growth over a silicon layer disposed on a substrate; implanting atoms to amorphize the silicon layer and a lower portion of the silicon germanium layer, without amorphizing a surface portion of the silicon germanium layer; and annealing, to at least partially relax the silicon germanium layer and to re-crystallize the lower portion of the silicon germanium layer and the silicon layer, so that the silicon layer becomes a strained silicon layer.
    Type: Application
    Filed: March 20, 2014
    Publication date: September 25, 2014
    Inventors: Aomar Halimaoui, Jean-Michel Hartmann
  • Patent number: 8486810
    Abstract: A layer of second semiconductor material is deposited on the layer of first semiconductor material of a substrate. Two active areas are then defined by means of selective elimination of the first and second semiconductor materials. One of the two active areas is then covered by a protective material. The layer of second semiconductor material is then eliminated by means of selective elimination of material. A first active area comprising a main surface made from a first semiconductor material, and a second active area comprising a main surface made from second semiconductor material are thus obtained.
    Type: Grant
    Filed: October 25, 2011
    Date of Patent: July 16, 2013
    Assignee: Commissariat a l'Energie Atomique et aux Energies Alternatives
    Inventor: Jean-Michel Hartmann
  • Publication number: 20120108019
    Abstract: A layer of second semiconductor material is deposited on the layer of first semiconductor material of a substrate. Two active areas are then defined by means of selective elimination of the first and second semiconductor materials. One of the two active areas is then covered by a protective material. The layer of second semiconductor material is then eliminated by means of selective elimination of material. A first active area comprising a main surface made from a first semiconductor material, and a second active area comprising a main surface made from second semiconductor material are thus obtained.
    Type: Application
    Filed: October 25, 2011
    Publication date: May 3, 2012
    Applicant: COMMISSARIAT A L'ENERGIE ATOMIQUE ET AUX ENERGIES ALTERNATIVES
    Inventor: Jean-Michel HARTMANN
  • Patent number: 8110460
    Abstract: A method for producing stacked and self-aligned components on a substrate, including: providing a substrate made of monocrystalline silicon having one face enabling production of components, forming a stack of layers on the face of the substrate, selective etching by a gaseous mixture comprising gaseous HCl conveyed by a carrier gas and at a temperature between 450° C. and 900° C., depositing resin, implementing lithography of the resin, replacing resin eliminated during the lithography with a material for confining remaining resin, and forming elements of the components.
    Type: Grant
    Filed: October 12, 2009
    Date of Patent: February 7, 2012
    Assignee: Commissariat a l'Energie Atomique
    Inventors: Romain Wacquez, Philippe Coronel, Vincent Destefanis, Jean-Michel Hartmann