Abstract: A method for producing a semiconductor-on-insulator type substrate includes epitaxial deposition of a first semiconductor layer on a smoothing layer supported by a monocrystalline support substrate to form a donor substrate; production of an assembly by contacting the donor substrate with a receiver substrate; transfer, onto the receiver substrate, of the first semiconductor layer, the smoothing layer and a portion of the support substrate; and selective etching of the portion of the support substrate relative to the smoothing layer. The epitaxial deposition of the first semiconductor layer can be preceded by a surface preparation annealing of the support substrate at a temperature greater than 650° C. After the selective etching of the portion of the support substrate, selective etching of the smoothing layer relative to the first semiconductor layer and epitaxial deposition of a second semiconductor layer on the first semiconductor layer may be carried out in an epitaxy frame.

Abstract: The fabrication of a first waveguide made of stoichiometric silicon nitride, of a second waveguide made of crystalline semiconductor material and of at least one active component optically coupled to the first waveguide via the second waveguide. The method includes: a) the formation of an aperture which passes through an encapsulation layer of the first waveguide and emerges in or on a substrate made of monocrystalline silicon, then b) the deposition by epitaxial growth of a crystalline seeding material inside the aperture until this crystalline seeding material forms a crystalline seed on a top face of the encapsulation layer, then c) a lateral epitaxy, of a crystalline semiconductor material from the crystalline seed formed to form a layer made of crystalline semiconductor material wherein the second waveguide is then produced.

Abstract: A planar photodiode including a main layer including an n-doped first region, a p-doped second region, and an intermediate region, and also a p-doped peripheral lateral portion. It also includes a peripheral intermediate portion, made of an alternation of monocrystalline thin layers of silicon-germanium and germanium, located on the first face, and extending between and at a non-zero distance from the doped first region and from the peripheral lateral portion so as to surround the doped first region in a main plane.

Abstract: A method of forming an opening in an insulating layer covering a semiconductor region including germanium, successively including: the forming of a first masking layer on the insulating layer; the forming on the first masking layer of a second masking layer including an opening; the etching of an opening in the first masking layer, in line with the opening of the second masking layer; the removal of the second masking layer by oxygen-based etching; and the forming of the opening of said insulating layer in line with the opening of the first masking layer, by fluorine-based etching.

Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.

Abstract: A process for hydrophilic bonding first and second substrates, comprising: —bringing the first and second substrates into contact to form a bonding interface between main surfaces of the first and second substrates, and —applying a heat treatment to close the bonding interface. The process further comprises, before the step of bringing into contact, depositing, on the main surface of the first and/or second substrate, a bonding layer comprising a non-metallic material that is permeable to dihydrogen and that has, at the temperature of the heat treatment, a yield strength lower than that of at least one of the materials of the first substrate and of the second substrate located at the bonding interface. The layer has a thickness between 1 and 6 nm, and the heat treatment is carried out at a temperature lower than or equal to 900° C., and preferably lower than or equal to 600° C.

Abstract: A method of forming an area of electric contact with a semiconductor region mainly made of germanium, comprising the forming of a first area made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms. There is also described a device including such a contacting area.

Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.

Abstract: A method for producing a semiconductor-on-insulator type substrate includes epitaxial deposition of a first semiconductor layer on a smoothing layer supported by a monocrystalline support substrate to form a donor substrate; production of an assembly by contacting the donor substrate with a receiver substrate; transfer, onto the receiver substrate, of the first semiconductor layer, the smoothing layer and a portion of the support substrate; and selective etching of the portion of the support substrate relative to the smoothing layer. The epitaxial deposition of the first semiconductor layer can be preceded by a surface preparation annealing of the support substrate at a temperature greater than 650° C. After the selective etching of the portion of the support substrate, selective etching of the smoothing layer relative to the first semiconductor layer and epitaxial deposition of a second semiconductor layer on the first semiconductor layer may be carried out in an epitaxy frame.

Abstract: A method of polishing a semiconductor substrate, including: a) a step of multiple implantations of ions from an upper surface of the substrate, to modify the material of an upper portion of the substrate, the multiple implantation step comprising a plurality of successive implantations under different respective implantation orientations; and b) a step of selective removal of the upper portion of the substrate.

Abstract: An optoelectronic device includes an array of germanium-based photodiodes including a stack of semiconductor layers, made from germanium, trenches, and a passivation semiconductor layer, made from silicon. Each photodiode includes a silicon-germanium peripheral zone in the semiconductor portion formed through an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of the semiconductor portion.

Abstract: A process for fabricating an optoelectronic device including an array of germanium-based photodiodes including the following steps: producing a stack of semiconductor layers, made from germanium; producing trenches; depositing a passivation intrinsic semiconductor layer, made from silicon; annealing, ensuring, for each photodiode, an interdiffusion of the silicon of the passivation semiconductor layer and of the germanium of a semiconductor portion, thus forming a peripheral zone of the semiconductor portion, made from silicon-germanium.

Abstract: A method for producing a waveguide including a germanium-based core and a cladding is provided, the method including a step of “low temperature” depositing of a shell after forming the core by engraving, such that the deposition temperature is less than 780° C., followed by a step of “high temperature” depositing of a thick encapsulation layer. The shell and the encapsulation layer at least partially form the cladding of the waveguide. Optionally, a step of annealing under hydrogen at a “low temperature”, less than 750° C., precedes the deposition of the shell. These “low temperature” annealing and depositing steps advantageously make it possible to avoid a post-engraving alteration of the free surfaces of the core during the forming of the cladding which is less germanium-rich.

Abstract: The invention relates to a method for manufacturing a waveguide (2a, 2b) comprising: A supplying of a substrate (1) comprising a stack of a first layer (11) based on a first material on a second layer (12) based on a second material, and at least one sequence successively comprising: An etching of the first material, in such a way as to define at least one pattern (20, 22a) having etching flanks (200, 201), A smoothing annealing assisted by hydrogen in such a way as to smooth the etching flanks (200, 201) of the at least one pattern (20, 22a), A re-epitaxy of the first material on the pattern (20, 22a) based on the first material.

Abstract: A method for the nanoscale etching of a layer of Ge1-xSnx on a carrier for a FET transistor, x being the concentration of tin in the GeSn alloy, the etching method includes a step of plasma-etching the layer of Ge1-xSnx using a mixture comprising dichlorine (Cl2) and dinitrogen (N2) and under an etching pressure lower than or equal to 50 mTorr, preferably lower than or equal to 10 mTorr. A method for producing a conduction channel on a carrier for a FET transistor, comprising a step of forming a layer of Ge1-xSnx on the carrier, the layer being produced by epitaxial growth, and a step of etching the layer of Ge1-xSnx according to the etching method. A conduction channel made of Ge1-xSnx for a FET transistor, the channel being obtained according to the production method, and a FET transistor comprising a plurality of conduction channels made of Ge1-xSnx.

Abstract: The invention relates to a method for manufacturing a waveguide (2a, 2b) comprising: A supplying of a substrate (1) comprising a stack of a first layer (11) based on a first material on a second layer (12) based on a second material, and at least one sequence successively comprising: An etching of the first material, in such a way as to define at least one pattern (20, 22a) having etching flanks (200, 201), A smoothing annealing assisted by hydrogen in such a way as to smooth the etching flanks (200, 201) of the at least one pattern (20, 22a), A re-epitaxy of the first material on the pattern (20, 22a) based on the first material

Abstract: A method of forming an opening in an insulating layer covering a semiconductor region including germanium, successively including: the forming of a first masking layer on the insulating layer; the forming on the first masking layer of a second masking layer including an opening; the etching of an opening in the first masking layer, in line with the opening of the second masking layer; the removal of the second masking layer by oxygen-based etching; and the forming of the opening of said insulating layer in line with the opening of the first masking layer, by fluorine-based etching.

Abstract: A method of forming an area of electric contact with a semiconductor region mainly made of germanium, comprising the forming of a first area made of a first intermetallic material where more than 70% of the non-metal atoms are silicon atoms. There is also described a device including such a contacting area.

Abstract: The invention pertains to a process for producing a strained layer based on germanium-tin (GeSn). The process includes a step of producing a semiconductor stack containing a layer based on GeSn and having an initial strain value that is non-zero; a step of structuring the semiconductor stack so as to form a structured portion and a peripheral portion, the structured portion including a central section linked to the peripheral portion by at least two lateral sections having an average width greater than an average width of the central section; and a step of suspending the structured portion, the central section then having a final strain value higher than the initial value.

Abstract: A substrate is provided with a monocrystalline silicon-germanium layer with a first surface covered by a protective oxide obtained by wet process and having a degradation temperature. The protective oxide is transformed into fluorinated salt which is then eliminated. The substrate is placed in a processing chamber at a lower temperature than the degradation temperature and is subjected to a temperature ramp up to a higher temperature than the degradation temperature. The first surface is annealed in a hydrogen atmosphere devoid of silicon, germanium and precursors of the materials forming the target layer. When the temperature ramp is applied, a silicon precursor is inserted in the processing chamber between a loading temperature and the degradation temperature to deposit a monocrystalline buffer layer. A mono-crystalline target layer is deposited by chemical vapour deposition.