Patents by Inventor Jean-Michel Mirabel
Jean-Michel Mirabel has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 9691866Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.Type: GrantFiled: August 30, 2016Date of Patent: June 27, 2017Assignee: STMicroelectronics (Rousset) SASInventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
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Publication number: 20160372561Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.Type: ApplicationFiled: August 30, 2016Publication date: December 22, 2016Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
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Patent number: 9461129Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.Type: GrantFiled: September 15, 2015Date of Patent: October 4, 2016Assignee: STMicroelectronics (Rousset) SASInventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
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Publication number: 20160181265Abstract: A memory cell formed in a semiconductor substrate, includes a selection gate extending vertically in a trench made in the substrate, and isolated from the substrate by a first layer of gate oxide, a horizontal floating gate extending above the substrate and isolated from the substrate by a second layer of gate oxide, and a horizontal control gate extending above the floating gate. The selection gate covers a lateral face of the floating gate. The floating gate is separated from the selection gate only by the first layer of gate oxide, and separated from a vertical channel region, extending in the substrate along the selection gate, only by the second layer of gate oxide.Type: ApplicationFiled: September 15, 2015Publication date: June 23, 2016Inventors: Arnaud Regnier, Jean-Michel Mirabel, Stephan Niel, Francesco La Rosa
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Patent number: 8995190Abstract: A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The sector includes at least two distinct wells insulated from one another, each including a number of cells of the sector, being able to take different potentials, and in that the sector has at least one bit line electrically linked to the drain of at least two cells mounted on two distinct wells.Type: GrantFiled: May 24, 2012Date of Patent: March 31, 2015Assignee: STMicroelectronics (Rousset) SASInventor: Jean-Michel Mirabel
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Patent number: 8426973Abstract: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.Type: GrantFiled: August 10, 2009Date of Patent: April 23, 2013Assignee: STMicroelectronics (Rousset) SASInventors: Stephan Niel, Jean-Michel Mirabel
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Publication number: 20120320681Abstract: A sector of an electrically programmable non-volatile memory includes memory cells connected to word lines and to bit lines, each cell including at least one transistor having a gate connected to a word line, a drain connected to a bit line and a source connected to a source line. The sector includes at least two distinct wells insulated from one another, each including a number of cells of the sector, being able to take different potentials, and in that the sector has at least one bit line electrically linked to the drain of at least two cells mounted on two distinct wells.Type: ApplicationFiled: May 24, 2012Publication date: December 20, 2012Applicant: STMicroelectronics (Rousset) SASInventor: Jean-Michel Mirabel
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Patent number: 7675106Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.Type: GrantFiled: September 22, 2006Date of Patent: March 9, 2010Assignees: STMicroelectronics S.A., STMicroelectronics SAS, France Universite d'Aix-MarseilleInventors: Rachid Bouchakour, Virginie Bidal, Philippe Candelier, Richard Fournel, Philippe Gendrier, Romain Laffont, Pascal Masson, Jean-Michel Mirabel, Arnaud Regnier
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Publication number: 20100044874Abstract: An integrated circuit including an insulating layer having first and second opposite surfaces. The circuit includes, in a first area, first conductive portions of a first conductive material, located in the insulating layer, flush with the first surface and continued by first vias of the first conductive material, of smaller cross-section and connecting the first conductive portions to the second surface. The circuit further includes, in a second area, second conductive portions of a second material different from the first conductive material and arranged on the first surface and second vias of the first conductive material, in contact with the second conductive portions and extending from the first surface to the second surface.Type: ApplicationFiled: August 10, 2009Publication date: February 25, 2010Applicant: STMicroelectronics (Rousset) SASInventors: Stephan Niel, Jean-Michel Mirabel
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Patent number: 7242621Abstract: The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.Type: GrantFiled: June 17, 2005Date of Patent: July 10, 2007Assignees: STMicroelectronics Rousset SAS, Universite d'Aix Marseille IInventors: Jean-Michel Mirabel, Arnaud Regnier, Rachid Bouchakour, Romain Laffont, Pascal Masson
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Publication number: 20070069278Abstract: A non-volatile memory point including a floating gate placed above a semiconductor substrate, the floating gate comprising active portions insulated from the substrate by thin insulating layers, and inactive portions insulated from the substrate by thick insulating layers that do not conduct electrons, the active portions being principally P-type doped, and the inactive portions comprising at least one N-type doped area forming a portion of a PN junction.Type: ApplicationFiled: September 22, 2006Publication date: March 29, 2007Applicants: STMicroelectronics S.A., STMicroelectronics (Rousset) SAS, FRANCE UNIVERSITE D'AIX-MARSEILLE IInventors: Rachid Bouchakour, Virginie Bidal, Philippe Candelier, Richard Fournel, Philippe Gendrier, Romain Laffont, Pascal Masson, Jean-Michel Mirabel, Arnaud Regnier
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Patent number: 7183160Abstract: The invention relates to a production process for a flash memory from a semi-conductor substrate fitted with at least two adjacent rows of precursor stacks of floating gate transistors, the precursor stacks being at least partially covered by a protective resin and being separated by a formation zone for a source line. The process includes forming a trench in the formation zone for the source line by an attack of this zone and of the protective resin. The result of the attack step includes a deposit of residue from the resin below the precursor stacks. The residue deposit is removed. A source line is implanted in the formation zone below the precursor stacks. This process enables the time needed for erasing the memory to be reduced.Type: GrantFiled: January 22, 2004Date of Patent: February 27, 2007Assignee: STMicroelectronics (Rousset) SASInventors: Olivier Pizzuto, Romain Laffont, Jean-Michel Mirabel
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Publication number: 20050286303Abstract: The present invention relates to a floating-gate MOS transistor, comprising drain and source regions implanted into a silicon substrate, a channel extending between the drain and source regions, a tunnel oxide, a floating gate, a gate oxide and a control gate extending according to a determined gate length. According to the present invention, the control gate comprises a small gate and a large gate arranged side by side and separated by an electrically insulating material. Application to the production of memory cells without access transistor, and to the implementation of an erase-program method with reduced electrical stress for the tunnel oxide.Type: ApplicationFiled: June 17, 2005Publication date: December 29, 2005Applicants: STMicroelectronics Rousset SAS, Universite d'Aix Marseille IInventors: Jean-Michel Mirabel, Arnaud Regnier, Rachid Bouchakour, Romain Laffont, Pascal Masson
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Publication number: 20050087816Abstract: The invention relates to a production process for a flash memory from a semi-conductor substrate fitted with at least two adjacent rows of precursor stacks of floating gate transistors, the precursor stacks being at least partially covered by a protective resin and being separated by a formation zone for a source line. The process includes forming a trench in the formation zone for the source line by an attack of this zone and of the protective resin. The result of the attack step includes a deposit of residue from the resin below the precursor stacks. The residue deposit is removed. A source line is implanted in the formation zone below the precursor stacks. This process enables the time needed for erasing the memory to be reduced.Type: ApplicationFiled: January 22, 2004Publication date: April 28, 2005Applicants: STMICROELECTRONICS SA, UNIVERSITE DE PROVENCEInventors: Olivier Pizzuto, Romain Laffont, Jean-Michel Mirabel
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Patent number: 6829170Abstract: A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.Type: GrantFiled: July 9, 2003Date of Patent: December 7, 2004Assignees: STMicroelectronics SA, Laboratoire Matériaux et Microélectronique de ProvenceInventors: Jean-Michel Mirabel, Rachid Bouchakour, Pierre Canet, Romain Laffont, Juliano Razafindramora
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Publication number: 20040057265Abstract: A memory cell in an EEPROM includes a floating gate transistor that includes a first conducting terminal and a control gate. A method of controlling the memory cell includes setting a state of the memory cell by simultaneously applying voltage pulses of opposite polarities respectively to the first conducting terminal and to the control gate. The voltage pulses including a first portion having a first slope and a second portion having a second slope, wherein the second slope is based upon the polarities of the voltage pulses. The method allows the amplitude of the voltage pulses to be reduced.Type: ApplicationFiled: July 9, 2003Publication date: March 25, 2004Applicants: STMicroelectronics SA, Laboratoire Materiaux et Microelectronique de Provence (L2MP)Inventors: Jean-Michel Mirabel, Rachid Bouchakour, Pierre Canet, Romain Laffont, Juliano Razafindramora
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Patent number: 6455386Abstract: The present invention relates to a method of manufacturing integrated circuits including high and low voltage MOS transistors. This method includes steps of forming insulated gate structure forming lightly-doped drain/source regions, depositing an insulating layer; forming a mask above the gates of the high voltage transistors which extends laterally beyond said gates; etching the insulating layer to leave spacers on the edges of the low voltage transistor gates; implanting a dopant adapted to forming heavily-doped drain/source contact regions of the high and low voltage transistors; and forming in a self-aligned way a metal silicide layer on the drain/source contact regions of all transistors, as well as on the gate contacts of the low voltage transistors.Type: GrantFiled: June 2, 1999Date of Patent: September 24, 2002Assignee: STMicroelectronics S.A.Inventor: Jean-Michel Mirabel
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Publication number: 20020089011Abstract: The present invention relates to an EEPROM cell with a single polysilicon level which corresponds to a floating gate which extends, on the one hand, via a first insulating layer above a heavily-doped region of a first type of conductivity forming a control gate, on the other hand, via a second insulating layer to form a gate finger above a channel area of the cell. The second insulating layer is a sufficiently thin layer to allow a tunnel effect and the drain area of the cell has a gradual profile and partially extends under the gate finger.Type: ApplicationFiled: June 15, 1998Publication date: July 11, 2002Inventor: JEAN-MICHEL MIRABEL
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Patent number: 6156609Abstract: The present invention relates to a method of manufacturing, in a P-type substrate including active areas separated by field oxide areas, heavily-doped stop-channel regions under portions of the field insulation areas, more lightly-doped P- and N-type areas meant to form MOS transistor wells, and heavily-doped N-type areas meant to form the first electrode of a capacitor, including the steps of performing a high energy N-type implantation in P-channel MOS transistor areas; performing a high energy P-type implantation in N-channel MOS transistor areas; performing a high energy P-type implantation in stop-channel areas and in capacitor areas; and performing a low energy N-type implantation, masked by the field oxide.Type: GrantFiled: April 23, 1999Date of Patent: December 5, 2000Assignee: STMicroelectronics S.A.Inventor: Jean-Michel Mirabel
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Patent number: 5737266Abstract: A method for the programming of floating-gate memory cells of a content-addressable memory in an integrated circuit comprises the application, through a programming path, of a programming high voltage to the drain of selected cells. The method comprises a verification stage in which the selection of these cells is maintained to obtain direct read access to these cells by applying a read voltage to them through said programming path and to carry out a measurement of current or of voltage on said programming path.Type: GrantFiled: October 25, 1996Date of Patent: April 7, 1998Assignee: SGS-Thomson Microelectronics S.A.Inventor: Jean-Michel Mirabel