Patents by Inventor Jean Patrice Rakotoniana
Jean Patrice Rakotoniana has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 8882912Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.Type: GrantFiled: February 25, 2011Date of Patent: November 11, 2014Assignee: Silicor Materials Inc.Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Publication number: 20110309478Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.Type: ApplicationFiled: August 26, 2011Publication date: December 22, 2011Applicant: Calisolar, Inc.Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke
-
Publication number: 20110211995Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.Type: ApplicationFiled: February 25, 2011Publication date: September 1, 2011Applicant: Calisolar, Inc.Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Patent number: 8008107Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.Type: GrantFiled: December 30, 2006Date of Patent: August 30, 2011Assignee: Calisolar, Inc.Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke
-
Patent number: 7955433Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.Type: GrantFiled: July 26, 2007Date of Patent: June 7, 2011Assignee: Calisolar, Inc.Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Patent number: 7651566Abstract: Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides a predominantly p-type semiconductor for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of aluminum or/and gallium. The process further melts the silicon feedstock together with a predetermined amount of aluminum or/and gallium to form a molten silicon solution from which to perform directional solidification and, by virtue of adding aluminum or/and gallium, maintains the homogeneity the resistivity of the silicon ingot throughout the silicon ingot. In the case of feedstock silicon leading to low resistivity in respective ingots, typically below 0.4 ?cm, a balanced amount of phosphorus can be optionally added to aluminum or/and gallium.Type: GrantFiled: June 27, 2007Date of Patent: January 26, 2010Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Publication number: 20090026423Abstract: Techniques for controlling resistivity in the formation of a silicon ingot from compensated feedstock silicon material prepares a compensated, upgraded metallurgical silicon feedstock for being melted to form a silicon melt. The compensated, upgraded metallurgical silicon feedstock provides a predominantly p-type semiconductor for which the process assesses the concentrations of boron and phosphorus and adds a predetermined amount of aluminum or/and gallium. The process further melts the silicon feedstock together with a predetermined amount of aluminum or/and gallium to form a molten silicon solution from which to perform directional solidification and, by virtue of adding aluminum or/and gallium, maintains the homogeneity the resistivity of the silicon ingot throughout the silicon ingot. In the case of feedstock silicon leading to low resistivity in respective ingots, typically below 0.4? cm, a balanced amount of phosphorus can be optionally added to aluminum or/and gallium.Type: ApplicationFiled: June 27, 2007Publication date: January 29, 2009Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Publication number: 20090028773Abstract: Techniques for the formation of a silicon ingot using a low-grade silicon feedstock include forming within a crucible device a molten silicon from a low-grade silicon feedstock and performing a directional solidification of the molten silicon to form a silicon ingot within the crucible device. The directional solidification forms a generally solidified quantity of silicon and a generally molten quantity of silicon. The method and system include removing from the crucible device at least a portion of the generally molten quantity of silicon while retaining within the crucible device the generally solidified quantity of silicon. Controlling the directional solidification of the generally solidified quantity of silicon, while removing the more contaminated molten silicon, results in a silicon ingot possessing a generally higher grade of silicon than the low-grade silicon feedstock.Type: ApplicationFiled: July 26, 2007Publication date: January 29, 2009Inventors: Fritz Kirscht, Vera Abrosimova, Matthias Heuer, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Publication number: 20080257254Abstract: Techniques for the formation of a large grain, multi-crystalline semiconductor ingot and include forming a silicon melt in a crucible, the crucible capable of locally controlling thermal gradients within the silicon melt. The local control of thermal gradients preferentially forms silicon crystals in predetermined regions within the silicon melt by locally reducing temperatures is the predetermined regions. The method and system control the rate at which the silicon crystals form using local control of thermal gradients for inducing the silicon crystals to obtain preferentially maximal sizes and, thereby, reducing the number of grains for a given volume. The process continues the thermal gradient control and the rate control step to form a multicrystalline silicon ingot having reduced numbers of grains for a given volume of the silicon ingot.Type: ApplicationFiled: April 17, 2007Publication date: October 23, 2008Inventors: Dieter Linke, Matthias Heuer, Fritz Kirscht, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Publication number: 20080197454Abstract: Techniques are here disclosed for a solar cell pre-processing. The method and system remove impurities from low-grade crystalline semiconductor wafers and include forming a low-grade semiconductor wafer having a substrate having high impurity content. The process and system damage at least one surface of the semiconductor wafer either in the semiconductor wafer forming step or in a separate step to form a region on the surface that includes a plurality of gettering centers. The gettering centers attract impurities from the substrate during subsequent processing. The subsequent processes include diffusing impurities from the substrate using a phosphorus gettering process that includes impregnating the surface with a phosphorus material for facilitating the formation of impurity clusters associated with the gettering centers.Type: ApplicationFiled: February 16, 2007Publication date: August 21, 2008Applicant: CaliSolar, Inc.Inventors: Jean Patrice Rakotoniana, Matthias Heuer, Fritz Kirscht, Dieter Linke, Kamel Ounadjela
-
Publication number: 20080178793Abstract: Techniques for the formation of a higher purity semiconductor ingot using a low purity semiconductor feedstock include associating within a crucible a low-grade silicon feedstock, which crucible forms a process environment of said molten silicon. The process associates with the low-grade silicon feedstock, a quantity of the at least one metal and includes forming within the crucible a molten solution (e.g., a binary or ternary solution) of molten silicon and the metal at a temperature below the melting temperature of said low-grade silicon feedstock. A silicon seed crystal associates with the molten solution within the crucible for inducing directional silicon crystallization. The process further forms a silicon ingot from a portion of the molten solution in association with the silicon seed. The silicon ingot includes at least one silicon crystalline formation grown in the induced directional silicon crystallization process.Type: ApplicationFiled: January 31, 2007Publication date: July 31, 2008Inventors: Matthias Heuer, Fritz Kirscht, Dieter Linke, Jean Patrice Rakotoniana, Kamel Ounadjela
-
Publication number: 20080157241Abstract: Techniques are here disclosed for a solar cell pre-processing method and system for annealing and gettering a solar cell semiconductor wafer having an undesirably high dispersion of transition metals, impurities and other defects. The process forms a surface contaminant layer on the solar cell semiconductor (e.g., silicon) wafer. A surface of the semiconductor wafer receives and holds impurities, as does the surface contaminant layer. The lower-quality semiconductor wafer includes dispersed defects that in an annealing process getter from the semiconductor bulk to form impurity cluster toward the surface contaminant layer. The impurity clusters form within the surface contaminant layer while increasing the purity level in wafer regions from which the dispersed defects gettered. Cooling follows annealing for retaining the impurity clusters and, thereby, maintaining the increased purity level of the semiconductor wafer in regions from which the impurities gettered.Type: ApplicationFiled: December 30, 2006Publication date: July 3, 2008Inventors: Fritz Kirscht, Kamel Ounadjela, Jean Patrice Rakotoniana, Dieter Linke