Patents by Inventor Jean-Paul Georges PONCELET

Jean-Paul Georges PONCELET has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10489306
    Abstract: A data processing system incorporates a cache system having a cache memory and a cache controller. The cache controller selects for cache entry eviction using a primary eviction policy. This primary eviction policy may identify a plurality of candidates for eviction with an equal preference for eviction. The cache controller provides a further selection among this plurality of candidates based upon content data read from those candidates themselves as part of the cache access operation which resulted in the cache miss leading to the cache replacement requiring the victim selection. The content data used to steer this second stage of victim selection may include transience specifying data and, for example, in the case of a cache memory comprising a translation lookaside buffer, page size data, type of translation data, memory type data, permission data and the like.
    Type: Grant
    Filed: May 17, 2016
    Date of Patent: November 26, 2019
    Assignee: ARM Limited
    Inventors: Guillaume Bolbenes, Jean-Paul Georges Poncelet
  • Publication number: 20170344492
    Abstract: A memory management unit 22, 34, 48 serves to use first stage of address translation and permission data S1 managed by a guest operating system and second stage of address translation and permission data S2 managed by a hypervisor. If there is a mismatch between the permissions (or other characteristics) provided by these different translation and permission data sets, then a speculative mismatch response is triggered. This speculative mismatch response may comprise storing a virtual address to intermediate physical address mapping within a cache 32, 36 within the memory management unit. Such a cache can subsequently be accessed by an instruction seeking to determine an intermediate physical address associated with a mismatch without having to wait for a full translation (page table walk) operation to be performed.
    Type: Application
    Filed: May 11, 2017
    Publication date: November 30, 2017
    Inventors: Guillaume BOLBENES, Jean-Paul Georges PONCELET
  • Publication number: 20170337133
    Abstract: A data processing system 2 incorporates a cache system 4 having a cache memory 6 and a cache controller 10, 12, 14, 16, 18. The cache controller selects for cache entry eviction using a primary eviction policy. This primary eviction policy may identify a plurality of candidates for eviction with an equal preference for eviction. The cache controller provides a further selection among this plurality of candidates based upon content data read from those candidates themselves as part of the cache access operation which resulted in the cache miss leading to the cache replacement requiring the victim selection. The content data used to steer this second stage of victim selection may include transience specifying data and, for example, in the case of a cache memory comprising a translation lookaside buffer 6, page size data, type of translation data, memory type data, permission data and the like.
    Type: Application
    Filed: May 17, 2016
    Publication date: November 23, 2017
    Inventors: Guillaume BOLBENES, Jean-Paul Georges PONCELET