Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.

Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.

Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.

Abstract: A method for transferring messages from a producer element to a consumer element uses a memory shared between the producer element and the consumer element, and a hardware queue including several registers designed to contain addresses of the shared memory. The method includes the steps of storing each message for the consumer element in the shared memory in the form of a node of a linked list, including a pointer to a next node in the list, the pointer being initially void, writing successively the address of each node in a free slot of the queue, whereby the node identified by each slot of the queue is the first node of a linked list assigned to the slot, and when the queue is full, writing the address of the current node in memory, in the pointer of the last node of the linked list assigned to the last slot of the queue, whereby the current node is placed at the end of the linked list assigned to the last slot of the queue.

Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A data stream flow-controller controls a transfer of data between a data processing device and an interconnection network. The flow controller includes interfaces for interfacing the controller on the network side and on the processing device side, a configurable storage for buffering queues of data in the controller before transfer to destination, and a programmable controller to control the storage to define queue parameters.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A process to make the cache memory of a processor consistent includes the processor processing a request to write data to an address in its memory marked as being in the shared state. The address is transmitted to the other processors, data are written into the processor's cache memory and the address changes to the modified state. An appended memory associated with the processor memorizes the address, the data and an associated marker in a first state. The processor then receives the address with an indicator. If the indicator indicates that the processor must perform the operation and if the associated marker is in the first state, the data are kept in the modified state. If the indicator does not indicate that the processor must perform the operation and if the processor receives an order to mark the data to be in the invalid state, the marker changes to a second state.

Abstract: A method of making cache memories of a plurality of processors coherent with a shared memory includes one of the processors determining whether an external memory operation is needed for data that is to be maintained coherent. If so, the processor transmits a cache coherency request to a traffic-monitoring device. The traffic-monitoring device transmits memory operation information to the plurality of processors, which includes an address of the data. Each of the processors determines whether the data is in its cache memory and whether a memory operation is needed to make the data coherent. Each processor also transmits to the traffic-monitoring device a message that indicates a state of the data and the memory operation that it will perform on the data. The processors then perform the memory operations on the data. The traffic-monitoring device performs the transmitted memory operations in a fixed order that is based on the states of the data in the processors' cache memories.

Abstract: A system comprises: a first execution unit, a second execution unit and a third execution unit; a first-in-first-out memory arranged to receive a plurality of instructions for the first to third execution units and to output the instructions to the execution units; a memory store for storing at least one instruction for one of the execution units, the at least one instruction being received from the first-in-first-out memory, the first and second execution units being arranged to receive their instructions from the first-in-first-out memory and the third execution unit being arranged to receive the instructions from the memory store, wherein a given instruction for the third execution unit is available to the third execution unit at substantially the same time that the instruction would be available to the first or second execution unit if that instruction was for the first or second execution unit.