Patents by Inventor Jean-Philippe Debray

Jean-Philippe Debray has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20210346530
    Abstract: A sterilization apparatus may include a cavity defined by walls of the apparatus. The sterilization apparatus may further include at least one internal compartment within the cavity. The internal compartment may include at least one reflective surface. The sterilization apparatus may also include one or more ultraviolet lights on a surface of at least one of the walls of the apparatus and directed toward the at least one internal compartment. The one or more ultraviolet lights may be configured to produce ultraviolet light in one or more of the UVB and UVC spectrums.
    Type: Application
    Filed: May 4, 2021
    Publication date: November 11, 2021
    Inventors: Jean-Philippe Debray, Chantal Arena, Robert Foster
  • Patent number: 9978905
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1?wN, and at least one barrier layer comprising InbGa1?bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1?wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1?bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: April 28, 2016
    Date of Patent: May 22, 2018
    Assignee: Soitec
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen
  • Patent number: 9634182
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: January 8, 2016
    Date of Patent: April 25, 2017
    Assignee: SOITEC
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
  • Publication number: 20160276530
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light-emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: April 28, 2016
    Publication date: September 22, 2016
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen
  • Patent number: 9397258
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer, and at least one barrier layer proximate the at least one well layer. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: July 30, 2015
    Date of Patent: July 19, 2016
    Assignee: SOITEC
    Inventors: Chantal Arena, Jean-Philippe Debray, Richard Scott Kern
  • Patent number: 9343626
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: May 17, 2016
    Assignee: SOITEC
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen
  • Publication number: 20160126410
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: January 8, 2016
    Publication date: May 5, 2016
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
  • Patent number: 9246057
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: January 26, 2016
    Assignee: SOITEC
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
  • Publication number: 20150333219
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer, and at least one barrier layer proximate the at least one well layer. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: July 30, 2015
    Publication date: November 19, 2015
    Inventors: Chantal Arena, Jean-Philippe Debray, Richard Scott Kern
  • Patent number: 9117955
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of fainting semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Grant
    Filed: March 14, 2014
    Date of Patent: August 25, 2015
    Assignee: SOITEC
    Inventors: Chantal Arena, Jean-Philippe Debray, Richard Scott Kern
  • Publication number: 20140264371
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Soitec
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen
  • Publication number: 20140264265
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of fainting semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Soitec
    Inventors: Chantal Arena, Jean-Philippe Debray, Richard Scott Kern
  • Publication number: 20140264408
    Abstract: Semiconductor structures include an active region between a plurality of layers of InGaN. The active region may be at least substantially comprised by InGaN. The plurality of layers of InGaN include at least one well layer comprising InwGa1-wN, and at least one barrier layer comprising InbGa1-bN proximate the at least one well layer. In some embodiments, the value of w in the InwGa1-wN of the well layer may be greater than or equal to about 0.10 and less than or equal to about 0.40 in some embodiments, and the value of b in the InbGa1-bN of the at least one barrier layer may be greater than or equal to about 0.01 and less than or equal to about 0.10. Methods of forming semiconductor structures include growing such layers of InGaN to form an active region of a light emitting device, such as an LED. Luminary devices include such LEDs.
    Type: Application
    Filed: March 14, 2014
    Publication date: September 18, 2014
    Applicant: Soitec
    Inventors: Jean-Philippe Debray, Chantal Arena, Heather McFavilen, Ding Ding, Li Huang
  • Publication number: 20060011938
    Abstract: Super lattice structures in conjunction with a tunnel junction to provide an improved contact for multiple components. The tunnel junctions can include a first semiconductor material having a resistance parameter for conducting a current and a second semiconductor material having a resistance parameter that is more restrictive to conduction of a current than the resistance parameter of the first semiconductor material. The first semiconductor material can have a critical thickness at which lattice matching of the first semiconductor material causes dislocation. The second semiconductor material can have a critical thickness at which lattice matching of the second semiconductor material causes dislocation that is thicker than the critical thickness of the first semiconductor material. The tunnel junction can be used in a monolithically manufactured photo transmitter and receiver design.
    Type: Application
    Filed: July 28, 2005
    Publication date: January 19, 2006
    Inventors: Jean-Philippe Debray, James Guenter