Patents by Inventor Jean-Philippe Fricker

Jean-Philippe Fricker has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10440860
    Abstract: A system for thermal management of a heat sink via active surfaces. The heat sink includes a cavity within the heat sink, and a nozzle. The nozzle provides a pathway from the cavity to a surface of the heat sink. The heat sink also includes a membrane attached to the cavity and an actuator of the membrane, causing the membrane to oscillate. The oscillation of the membrane causes inflow and outflow of a medium through the nozzle.
    Type: Grant
    Filed: September 30, 2015
    Date of Patent: October 8, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Jean-Philippe Fricker
  • Patent number: 10366967
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Grant
    Filed: June 27, 2018
    Date of Patent: July 30, 2019
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Patent number: 10361172
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Grant
    Filed: October 24, 2018
    Date of Patent: July 23, 2019
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Patent number: 10332860
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Grant
    Filed: October 29, 2018
    Date of Patent: June 25, 2019
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Patent number: 10321586
    Abstract: A system including a chassis and a hardware module bay disposed in a front portion of the chassis. The hardware module bay is configured to accommodate one or more horizontally oriented hardware modules. The one or more horizontally oriented hardware module are slidably insertable into the hardware module bay. The system further includes a main printed circuit board (PCB) that includes a chipset for communication with a hardware module inserted into the hardware module bay and a midplane disposed between the main PCB and the hardware module bay. The midplane is configured to electrically interface the hardware module inserted into the hardware module bay with the main PCB, upon insertion of the at least one horizontally oriented hardware module.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: June 11, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Jean-Philippe Fricker
  • Publication number: 20190172736
    Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.
    Type: Application
    Filed: February 5, 2019
    Publication date: June 6, 2019
    Inventors: Jean-Philippe Fricker, Frank Jun, Paul Kennedy
  • Publication number: 20190155702
    Abstract: A system for transmission of memory entries. The system includes a computing device that includes a memory module, a memory controller interfacing with the memory module via a memory bus, a snooping module interfacing with the memory bus, functionally in parallel to the memory module, and a high-speed interconnect, functionally connecting the snooping module to a receiving device. The memory controller is configured to write a memory entry to the memory module via the memory bus. The snooping module is configured to capture a copy of the memory entry being written to the memory module and to send the copy of the memory entry to the receiving device, via the high-speed interconnect.
    Type: Application
    Filed: January 25, 2019
    Publication date: May 23, 2019
    Inventor: Jean-Philippe Fricker
  • Publication number: 20190157243
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Application
    Filed: January 18, 2019
    Publication date: May 23, 2019
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Patent number: 10242891
    Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements.
    Type: Grant
    Filed: August 7, 2018
    Date of Patent: March 26, 2019
    Assignee: Cerebras Systems Inc.
    Inventors: Jean-Philippe Fricker, Frank Jun, Paul Kennedy
  • Patent number: 10235253
    Abstract: A system for transmission of memory entries. The system includes a computing device that includes a memory module, a memory controller interfacing with the memory module via a memory bus, a snooping module interfacing with the memory bus, functionally in parallel to the memory module, and a high-speed interconnect, functionally connecting the snooping module to a receiving device. The memory controller is configured to write a memory entry to the memory module via the memory bus. The snooping module is configured to capture a copy of the memory entry being written to the memory module and to send the copy of the memory entry to the receiving device, via the high-speed interconnect.
    Type: Grant
    Filed: January 8, 2018
    Date of Patent: March 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Jean-Philippe Fricker
  • Patent number: 10235314
    Abstract: A storage system including a hardware module slot, configured to mechanically accommodate a first hardware module. The hardware module slot includes a hardware module data connector configured to electrically interface with the first hardware module inserted into the hardware module slot. The storage system further includes a fabric that includes a first switch. The first switch includes a first protocol interface to the hardware module data connector and is configured to enable first protocol communications between the first hardware module and a second hardware module. The fabric also includes a second switch that includes a second protocol interface to the hardware module data connector and is configured to enable second protocol communications between the first hardware module and the second hardware module.
    Type: Grant
    Filed: December 28, 2015
    Date of Patent: March 19, 2019
    Assignee: EMC IP Holding Company LLC
    Inventor: Jean-Philippe Fricker
  • Publication number: 20190074262
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Application
    Filed: October 29, 2018
    Publication date: March 7, 2019
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Publication number: 20190067052
    Abstract: Systems and methods of securing an integrated circuit assembly includes: arranging a plurality of securing elements within a plurality of orifices fabricated within one or more layer components of a plurality of layer components of an integrated circuit assembly; applying a mechanical compression load against the integrated circuit assembly that uniformly compresses together the plurality of layer components of the integrated circuit assembly; after applying the mechanical compression load to the integrated circuit assembly, fastening the plurality of securing elements while the integrated circuit assembly is in a compressed state based on the mechanical compression load; and terminating the application of the mechanical compression load against the integrated circuit assembly based on the fastening of the plurality of securing elements
    Type: Application
    Filed: August 7, 2018
    Publication date: February 28, 2019
    Inventors: Jean-Philippe Fricker, Frank Jun, Paul Kennedy
  • Publication number: 20190057953
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Application
    Filed: October 24, 2018
    Publication date: February 21, 2019
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Publication number: 20190027460
    Abstract: An integrated circuit assembly that includes a semiconductor wafer having a first coefficient of thermal expansion; an electronic circuit substrate having a second coefficient of thermal expansion that is different than the first coefficient of thermal expansion; and an elastomeric connector arranged between the semiconductor wafer and the electronic circuit substrate and that forms an operable signal communication path between the semiconductor wafer and the electronic circuit substrate.
    Type: Application
    Filed: July 6, 2018
    Publication date: January 24, 2019
    Inventor: Jean-Philippe Fricker
  • Publication number: 20190027466
    Abstract: A semiconductor and a method of fabricating the semiconductor having multiple, interconnected die including: providing a semiconductor substrate having a plurality of disparate die formed within the semiconductor substrate, and a plurality of scribe lines formed between pairs of adjacent die of the plurality of disparate die; and fabricating, by a lithography system, a plurality of inter-die connections that extend between adjacent pair of die of the plurality of die.
    Type: Application
    Filed: June 27, 2018
    Publication date: January 24, 2019
    Inventors: Jean-Philippe Fricker, Philip Ferolito
  • Patent number: 10178806
    Abstract: A universal quick-disconnect fan tray for air cooling of field replaceable electronic units within a rack-mount enclosure comprises a pair of fan modules mounted in parallel on an intermediate printed circuit board for providing a unidirectional air flow through the enclosure. The printed circuit board has asymmetrically located spring-loaded pogo pin electrical contacts and a pogo pin mechanical locator for respectively engaging cooperating front or rear electrical pads and cooperating front and rear locator features within the enclosure for correctly locating and providing electrical connections to the fan tray and that afford quick connect and disconnect. The locations of the cooperating pads and features enable the fan tray to be translatable without being rotated from the front to the rear of the enclosure to maintain same direction of airflow.
    Type: Grant
    Filed: December 21, 2015
    Date of Patent: January 8, 2019
    Assignee: EMC IP Holding Company, LLC
    Inventor: Jean-Philippe Fricker
  • Patent number: 10158530
    Abstract: A cluster computer server is configured after a system reset or other configuration event. Each node of a fabric of the cluster compute server is employed, for purposes of configuration, as a cell in a cellular automaton, thereby obviating the need for a special configuration network to communicate configuration information from a central management unit. Instead, the nodes communicate configuration information using the same fabric interconnect that is used to communicate messages during normal execution of software services at the nodes.
    Type: Grant
    Filed: August 18, 2014
    Date of Patent: December 18, 2018
    Assignee: Advanced Micro Devices, Inc.
    Inventors: Michael E. James, Jean-Philippe Fricker
  • Patent number: 9996120
    Abstract: A printed circuit board (PCB) module that includes a processor package, an upper PCB and a lower PCB. The processor package includes a processor substrate and a processor. An upper socket is disposed on a lower surface of the upper PCB, and the upper socket electrically connects to a top electrical interface on the upper surface of the processor substrate. The lower PCB electrically interfaces with a bottom electrical interface on a lower surface of the processor substrate.
    Type: Grant
    Filed: March 31, 2016
    Date of Patent: June 12, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Jean-Philippe Fricker
  • Patent number: 9898375
    Abstract: A system for transmission of memory entries. The system includes a computing device that includes a memory module, a memory controller interfacing with the memory module via a memory bus, a snooping module interfacing with the memory bus, functionally in parallel to the memory module, and a high-speed interconnect, functionally connecting the snooping module to a receiving device. The memory controller is configured to write a memory entry to the memory module via the memory bus. The snooping module is configured to capture a copy of the memory entry being written to the memory module and to send the copy of the memory entry to the receiving device, via the high-speed interconnect.
    Type: Grant
    Filed: December 22, 2015
    Date of Patent: February 20, 2018
    Assignee: EMC IP Holding Company LLC
    Inventor: Jean-Philippe Fricker