Abstract: A memory management device includes circuits having a DCh base activate in a set of N circular commands, h successive commands among the set of commands. A device DCh activates h columns among K: S.sub.0, . . . , S.sub.K-1. A device DC2 activates two line sections among 2L: S'.sub.0, S".sub.0, . . . , S'.sub.L-1, S".sub.L-1. The device DC2 is dependent upon a condition C.sub.d which indicates if a limit d is exceeded by the activated columns, in which case the activation goes from S'.sub.i and S".sub.i and S'.sub.i+1, or else from S".sub.i and S'.sub.i+1 to S'.sub.i+1 and S".sub.i+1 and so on. Selection of groups of memory cells in a matrix-organized field is by high and low addresses transmitted to the devices DC2 and DCh by means of buses B.sub.L and B.sub.K.