Patents by Inventor Jean-Philippe Meunier
Jean-Philippe Meunier has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11962252Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.Type: GrantFiled: September 8, 2021Date of Patent: April 16, 2024Assignee: NXP USA, Inc.Inventors: Jean-Christophe Patrick Rince, Maxime Clairet, Erik Santiago, Jean-Philippe Meunier, Antoine Fabien Dubois
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Publication number: 20240053808Abstract: A semiconductor circuit is disclosed, comprising: a processor; a supply-voltage terminal arranged to receive a supply voltage; an out-of-range-voltage-detection circuit, coupled to the supply-voltage terminal and configured to output a voltage-out-of-range indicator in response to detecting that the supply voltage is out-of-range; a PWM signal generator configured to generate a PWM signal; a power-on-reset request terminal arranged to output the PWM signal during a normal operation of the processor; and logic circuitry between the signal generator and the POR request terminal and configured to modify the PWM signal in response receiving the voltage-out-of-range indicator. A microcontroller circuit incorporating such a semiconductor circuit, and a PMIC circuit for use in conjunction, are also disclosed.Type: ApplicationFiled: July 20, 2023Publication date: February 15, 2024Inventors: Alaa Eldin Y. El Sherif, Jean-Philippe Meunier, Loic Hureau, Thomas Henry Luedeke, Maxime Clairet
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Publication number: 20230185322Abstract: Monitoring for an over-voltage condition based on a regulated voltage is disclosed. A first terminal of a voltage regulator receives a first voltage which is based on a regulated voltage input to a controller. A second terminal of the voltage regulator receives a second voltage indicative of the voltage input to the controller. A determination is made whether the first voltage exceeds the first voltage reference for a first time window and the controller is reset based on the determination that the first voltage exceeds the first voltage reference. A determination is also made whether the second voltage exceeds the second voltage reference for the second time window and the voltage regulator is powered down on based on the determination that the second voltage exceeds the second voltage reference.Type: ApplicationFiled: December 7, 2022Publication date: June 15, 2023Inventors: Loic Hureau, Maxime Clairet, Alaa Eldin Y. El Sherif, Jean-Philippe Meunier, Thomas Henry Luedeke
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Patent number: 11577617Abstract: A dynamic safe state control circuit is disclosed that controls an electrical motor based on vehicle speed. A microcontroller or other processing device is configured to control an inverter system of an electrical motor. The dynamic safe state control circuit is configured to receive a first signal that corresponds to a speed of the electric motor. The circuit is configured to activate any one of a plurality of safe states in the inverter system based on the first signal and in response to a malfunction in the microcontroller.Type: GrantFiled: March 18, 2021Date of Patent: February 14, 2023Assignee: NXP USA, Inc.Inventors: Erik Santiago, Jean-Christophe Patrick Rince, Antoine Fabien Dubois, Maxime Clairet, Jean-Philippe Meunier
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Patent number: 11502506Abstract: An apparatus is disclosed that in one embodiment includes a circuit configured to selectively activate a transistor. The circuit is further configured to assert a signal when the circuit detects an electrical short between terminals of the transistor or when the circuit detects the transistor does not conduct current while the transistor is activated by the circuit. The circuit is further configured to output another signal, which is set to a first state or a second state. The other signal is set to the first state when the circuit detects the electrical short. The other signal is set to the second state when the circuit detects the transistor does not conduct current while activated.Type: GrantFiled: September 15, 2020Date of Patent: November 15, 2022Assignee: NXP USA, Inc.Inventors: Jean-Christophe Patrick Rince, Jean-Philippe Meunier, Erik Santiago, Antoine Fabien Dubois, Maxime Clairet
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Patent number: 11500403Abstract: A system-on-a-chip (SoC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high-stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system.Type: GrantFiled: March 17, 2021Date of Patent: November 15, 2022Assignee: NXP USA, INC.Inventors: Jean-Philippe Meunier, Maxime Clairet, Alaa Eldin Y El Sherif, Pierre Turpin
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Patent number: 11481280Abstract: Various embodiments relate to a distributed power system, including: a primary power management integrated circuit (PMIC) configured to receive a source voltage and connected to a primary communication bus, wherein the primary PMIC produces a secondary voltage on a voltage line, wherein the primary PMIC communicates with a microcontroller unit (MCU) via the primary communication bus; and a plurality of secondary PMICs connected to the primary PMIC via the voltage line, a secondary communication bus, and a fail line, wherein the plurality of secondary PMICs are configured to produce a pulsed signal on the fail line when a secondary PMIC fails, wherein the pulsed signal produced by each of the plurality of secondary PMICs have a unique pulse width that indicates to the primary PMIC the identity of the failed secondary PMIC.Type: GrantFiled: April 13, 2021Date of Patent: October 25, 2022Assignee: NXP USA, Inc.Inventors: Jean-Philippe Meunier, Maxime Clairet, Guillaume Jean Founaud, Alaa Eldin Y El Sherif
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Patent number: 11455026Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.Type: GrantFiled: August 21, 2020Date of Patent: September 27, 2022Assignee: NXP USA, Inc.Inventors: Loic Hureau, Jean-Philippe Meunier, Daniel McKenna
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Publication number: 20220265871Abstract: A composition of microparticles includes a non-radioactive and a radioactive isotope, and an injection vehicle, for use in the intratumoral treatment of cancer, by combined antitumoral effect of radioactivity and intratumoral microparticle deposition. The antitumoral effect provided by the cytotoxicity of radioactivity is enhanced by a modulation of the tumoral immune response induced by microparticle deposition inside the tumor, thereby decreasing the dose of radioactivity required to treat solid tumors. A method of treating solid tumors using a sub-optimal tumor-volume coverage dose of radioactivity combined with intratumoral microparticle deposition as a mean of tumor control is also disclosed.Type: ApplicationFiled: June 15, 2020Publication date: August 25, 2022Inventors: Ilyes Zahi, Valeria Muzio, Maurizio Mariani, Jean-Philippe Meunier, Mehrdad Khosh Nevis, Claude Carozzo, Frédérique Ponce
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Publication number: 20220253358Abstract: Various embodiments relate to a distributed power system, including: a primary power management integrated circuit (PMIC) configured to receive a source voltage and connected to a primary communication bus, wherein the primary PMIC produces a secondary voltage on a voltage line, wherein the primary PMIC communicates with a microcontroller unit (MCU) via the primary communication bus; and a plurality of secondary PMICs connected to the primary PMIC via the voltage line, a secondary communication bus, and a fail line, wherein the plurality of secondary PMICs are configured to produce a pulsed signal on the fail line when a secondary PMIC fails, wherein the pulsed signal produced by each of the plurality of secondary PMICs have a unique pulse width that indicates to the primary PMIC the identity of the failed secondary PMIC.Type: ApplicationFiled: April 13, 2021Publication date: August 11, 2022Inventors: Jean-Philippe Meunier, Maxime Clairet, Guillaume Jean Founaud, Alaa Eldin Y. El Sherif
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Publication number: 20220131477Abstract: An apparatus to insure safe behavior in an inverter system. In one embodiment, the apparatus includes a first high side gate driver, a first low side gate driver, a microcontroller configured to control the first high side and low side gate drivers. A voltage regulator provides a supply voltage to the microcontroller. A first pair of high side voltage regulators provide a first pair of high side supply voltages to the first high side gate driver. A first pair of low side voltage regulators provide a first pair of low side supply voltages to the first low side gate driver.Type: ApplicationFiled: September 8, 2021Publication date: April 28, 2022Inventors: Jean-Christophe Patrick Rince, Maxime Clairet, Erik Santiago, Jean-Philippe Meunier, Antoine Fabien Dubois
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Publication number: 20210365098Abstract: A power management device is disclosed comprising a power management processing unit and a safety unit; the power management processing unit comprising: a plurality of power units each configured to supply current from an input, and a main sequencer configured to implement a power-up sequence in and a power-down; the safety unit comprising: voltage monitors each configured to monitor the output voltage of a power unit; wherein the safety unit further comprises a safety sequencer configured to store sequence data; and wherein the safety unit further comprises a safety processing unit, configured to use the sequence data stored in the safety sequencer to monitor the plurality of power units during the power-up sequence by means of the respective voltage monitors. Associated systems and methods are also disclosed.Type: ApplicationFiled: May 6, 2021Publication date: November 25, 2021Inventors: Loic Hureau, Jean-Philippe Meunier
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Patent number: 11175723Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.Type: GrantFiled: April 20, 2020Date of Patent: November 16, 2021Assignee: NXP USA, Inc.Inventors: Loic Hureau, Daniel McKenna, Jean-Philippe Meunier, Thomas Henry Luedeke
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Publication number: 20210331591Abstract: A dynamic safe state control circuit is disclosed that controls an electrical motor based on vehicle speed. A microcontroller or other processing device is configured to control an inverter system of an electrical motor. The dynamic safe state control circuit is configured to receive a first signal that corresponds to a speed of the electric motor. The circuit is configured to activate any one of a plurality of safe states in the inverter system based on the first signal and in response to a malfunction in the microcontroller.Type: ApplicationFiled: March 18, 2021Publication date: October 28, 2021Inventors: Erik Santiago, Jean-Christophe Patrick Rince, Antoine Fabien Dubois, Maxime Clairet, Jean-Philippe Meunier
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Publication number: 20210294363Abstract: A system-on-a-chip (SoC) is designed to operate within optimal voltage and frequency ranges. If an SoC is provided power outside of the optimal voltage range, the SoC can be placed in a high-stress state, exposing the chip to a security attack. Embodiments of the present systems and method limit the minimum and maximum voltage supplied to an SoC from a power management integrated circuit (PMIC). Embodiments can also track a number of requests to provide power outside of the optimal range and can signal a warning of repeated attempts to take an SoC outside of the SoC's optimal range, which may be indicative of a malicious attack on the system.Type: ApplicationFiled: March 17, 2021Publication date: September 23, 2021Inventors: Jean-Philippe Meunier, Maxime Clairet, Alaa Eldin Y. El Sherif, Pierre Turpin
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Publication number: 20210111621Abstract: An apparatus is disclosed that in one embodiment includes a circuit configured to selectively activate a transistor. The circuit is further configured to assert a signal when the circuit detects an electrical short between terminals of the transistor or when the circuit detects the transistor does not conduct current while the transistor is activated by the circuit. The circuit is further configured to output another signal, which is set to a first state or a second state. The other signal is set to the first state when the circuit detects the electrical short. The other signal is set to the second state when the circuit detects the transistor does not conduct current while activated.Type: ApplicationFiled: September 15, 2020Publication date: April 15, 2021Inventors: Jean-Christophe Patrick Rince, Jean-Philippe Meunier, Erik Santiago, Antoine Fabien Dubois, Maxime Clairet
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Publication number: 20210089114Abstract: A cascaded power system including master power management circuitry and slave power management circuitry. The master circuitry includes a master power regulator, comparator circuitry, and control circuitry. The power regulator provides a supply voltage during a normal mode and discharges the supply voltage during a low power mode. The slave circuitry provides a core voltage when enabled and otherwise discharges the core voltage. The comparator circuitry monitors the voltage levels of the supply and core voltages and the control circuitry performs handshaking with the slave circuitry based partly on the voltages to ensure smooth transitioning between the normal and low power modes. The control circuitry asserts a low power good signal when the supply and core voltages are discharged, and de-asserts the low power good signal when the supply and core voltages are fully charged. A processor may rely on the low power mode signal for transitioning between power modes.Type: ApplicationFiled: August 21, 2020Publication date: March 25, 2021Inventors: Loic Hureau, Jean-Philippe Meunier, Daniel McKenna
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Publication number: 20200371581Abstract: A system and method of power mode management for a processor providing safe and robust transitioning between normal and low power modes to meet low current requirements and to ensure accurate power mode transition communications. A two step process includes receiving a digital code, starting a standby entry timer, and receiving a low power request indication before timeout of the standby entry timer to ensure a valid request, and otherwise resetting upon timer timeout. A watchdog timer ensures that a maximum standby duration is not exceeded. An acknowledge timer ensures valid communication between modules of a power management IC. Memory elements ensure and maintain valid states of reset and safe state pins during standby. Self tests are performed in which test failure prevents transition to the low power mode. A power good indication ensures the processor that the supply voltages are suitable for both low power and normal operation.Type: ApplicationFiled: April 20, 2020Publication date: November 26, 2020Inventors: Loic Hureau, Daniel McKenna, Jean-Philippe Meunier, Thomas Henry Luedeke
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Patent number: 8372997Abstract: According to the invention, powders of low hygroscopicity are prepared by granulation of an aqueous solution (1) in a fluidized bed (140). A compound formed from crystalline grains whose moisture content is defined and stable is obtained. The invention applies especially to organometallic complexes of glycine with a metal.Type: GrantFiled: August 17, 2009Date of Patent: February 12, 2013Assignee: Pancosma Societe Anonyme pour l'Industrie des Produits BiochimiquesInventors: Jean-Philippe Meunier, Sébastien Oguey
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Publication number: 20110171343Abstract: The invention relates to an additive, particularly for promoting food intake and the growth of animals such as piglets. Said additive is in the form of granules, each including: a core that includes at least one compound selected from taste modifiers, taste enhancers, and flavors; and a coating that includes at least two flavors. The invention also relates to a method for preparing such an additive.Type: ApplicationFiled: August 18, 2009Publication date: July 14, 2011Inventors: Jean-Philippe Meunier, Christelle Raulet, David Bravo