Abstract: Embodiments of a callback procedure mechanism and method are disclosed in relation to a system running a physics simulation in parallel with a main application. A main application registers callback procedures in memory shared with the physics simulation in response to data generated by the physics simulation. The callback procedures are executed by the physics simulation with data generated by the physics simulation.

Abstract: A PPU enhanced system stores software packages implementing, at least in part, a physics subroutine. The package being implemented as a plurality of modules, at least one module being stored and executed on a host system and another module being stored and executed on the PPU.

Abstract: An integrated circuit comprises an external memory, a plurality of parallel connected Vector Processing Engines (VPEs), and an External Memory Unit (EMU) providing a data transfer path between the VPEs and the external memory. Each VPE contains a plurality of data processing units and a message queuing system adapted to transfer messages between the data processing units and other components of the integrated circuit.

Abstract: A system and method of providing physics data generated by a physics simulation and consumed by main application are provided. The main application may incorporate different scene versions or varying physics-based complexity while running on systems having different hardware and software resources.

Abstract: A PPU enhanced system stores software packages implementing, at least in part, a physics subroutine. The package being implemented as a plurality of modules, at least one module being stored and executed on a host system and another module being stored and executed on the PPU.

Abstract: A method and device for controlling bandwidth distribution through a switch fabric is provided wherein a plurality of line cards and processor cards are connected through a switch fabric for parallel processing of transmission requests, along with the provision of transmission “credits” allowing for transmitting additional data bytes during a given cycle, which provides efficient and speedy bandwidth distribution, as well as resolution of output contentions. The processors maintain a credit balance which allows flexibility in granting transmission requests to accommodate transmission scheduling and “bursty” transmissions. Processors on both of the line cards and the processor cards normalize the data transmission requirements for both inputs and outputs connected by the switch fabric. Smoothing of data transmission is provided using a time-weighted buffer.