Patents by Inventor Jean-Pierre Dolait
Jean-Pierre Dolait has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20030196069Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196070Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196034Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: May 30, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030196068Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: June 2, 2003Publication date: October 16, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20030037219Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asychronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: ApplicationFiled: July 5, 2002Publication date: February 20, 2003Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6418078Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: December 21, 2000Date of Patent: July 9, 2002Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Publication number: 20010000817Type: ApplicationFiled: December 21, 2000Publication date: May 3, 2001Inventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 6188635Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: February 13, 2001Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5805518Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and ouput data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: September 8, 1998Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5768205Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is desclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof as permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: June 16, 1998Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5684753Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: November 4, 1997Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5680367Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5680358Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36), which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5680369Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data parts (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5680370Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronous read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5680368Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: October 21, 1997Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John Victor Moravec, Jean-Pierre Dolait
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Patent number: 5636176Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disabled. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: December 22, 1994Date of Patent: June 3, 1997Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John V. Moravec, Jean-Pierre Dolait
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Patent number: 5587962Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: June 7, 1995Date of Patent: December 24, 1996Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John V. Moravec, Jean-Pierre Dolait
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Patent number: 5400288Abstract: A memory circuit (14) having features specifically adapted to permit the memory circuit (14) to serve as a video frame memory is disclosed. The memory circuit (14) contains a dynamic random access memory array (24) with buffers (18, 20) on input and output data ports (22) thereof to permit asynchronious read, write and refresh accesses to the memory array (24). The memory circuit (14) is accessed both serially and randomly. An address generator (28) contains an address buffer register (36) which stores a random access address and an address sequencer (40) which provides a stream of addresses to the memory array (24). An initial address for the stream of addresses is the random access address stored in the address buffer register (36).Type: GrantFiled: December 29, 1993Date of Patent: March 21, 1995Assignee: Texas Instruments IncorporatedInventors: Masashi Hashimoto, Gene A. Frantz, John V. Moravec, Jean-Pierre Dolait