Abstract: An inverse discrete cosine transform calculation processor, for processing television picture signals, comprises a processor module consisting of four successive stages. The first stage comprises a multiplier associated with a sine and cosine function value store which is connected to one of its input buses. Each of the other three stages comprises an adder/subtracter having two input buses each selectively connected to the output bus of the directly preceding stage or to the output bus of an input register of this stage also loaded from the output bus of the directly preceding stage and which features on the output bus of one of the input registers of the fourth stage an internal loopback bus which with an input bus of the module is selectively connected to the second input bus of the multiplier.

Abstract: A discrete cosine transform calculation processor, suitable for compressing a television signal, comprises a processor module consisting of four successive stages. The first stage, the input stage of the module, comprises a first adder/subtracter. The second stage comprises a second adder/subtracter with two input buses each selectively connected to an output bus of the first stage or to an output bus of an input register of the second stage, loaded from an output bus of the first or fourth stage. The third stage comprises a multiplier connected to a cosine/sine function value store and to an output bus of the second stage. The fourth stage, the module output stage, comprises a third adder/subtracter with two input buses each selectively connected to an output bus of the third stage or to an output bus of an input register of this stage loaded from the multiplier.