Abstract: A novel method makes it possible to form cavities intended to contain a liquid with determined optical properties within a film for optical use. The walls (38) of the cavities (40) are formed by plasma etching of a layer of transparent or light absorbent material (30, 34) transferred onto a microtechnological substrate, the walls (38) having a structured profile in order to limit the parasitic phenomena of light diffusion and diffraction.

Abstract: A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Abstract: A novel method makes it possible to form cavities intended to contain a liquid with determined optical properties within a film for optical use. The walls (38) of the cavities (40) are formed by plasma etching of a layer of transparent or light absorbent material (30, 34) transferred onto a microtechnological substrate, the walls (38) having a structured profile in order to limit the parasitic phenomena of light diffusion and diffraction.

Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

Abstract: The three-dimensional integrated CMOS circuit is formed in a hybrid substrate. n-MOS type transistors are formed, at a bottom level, in a first semi-conducting layer of silicon having a (100) orientation, which layer may be tension strained. p-MOS transistors are formed, at a top level, in a preferably monocrystalline and compression strained second semi-conducting layer of germanium having a (110) orientation. The second semi-conducting layer is transferred onto a first block in which the n-MOS transistors were previously formed, and the p-MOS transistors are then formed.

Abstract: A process for producing a MOS-type transistor includes providing a substrate comprising a thin layer of silicon (26), integral with an insulating support (14), and covered with a superficial layer (28) of a semi-conductor material, local etching of the superficial layer to expose the silicon layer in at least one channel region, formation of an insulated gate (50) above the silicon layer in the channel region, and formation of a source and a drain on either side of the channel region, the source and drain extending in the layer of silicon and in the superficial layer.

Abstract: A method of fabricating a die containing an integrated circuit, including active components and passive components, includes producing a first substrate containing at least one active component of active components and a second substrate containing critical components of the passive components, such as perovskites or MEMS, and bonding the two substrates by a layer transfer. The method provides an improved monolithic integration of devices such as MEMS with transistors.

Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

Abstract: The present invention relates to process for producing a transistor of MOS type, comprising the following stages:

Abstract: The invention concerns a pressure sensor (1), able to operate at high temperature and measure the pressure of a hostile medium, comprising: a sensing element (4) integrating a membrane (8) in monocrystalline silicon carbide, made by micro-machining a substrate in polycrystalline silicon carbide, a first surface of membrane (8) intended to contact said medium, a second surface of membrane (8) comprising membrane deformation detection means (9) connected to electric contacts (10) to connect electric connection means (11), the surfaces of sensing element (4) contacting said medium being chemically inert to this medium; a carrier (5) to support sensing element (4) so that said first surface of membrane (8) may be contacted with said medium and the second surface of membrane (8) may be shielded from said medium, carrier (5) being in polycrystalline silicon carbide; a seal strip (6), in material containing silicon carbide, brazed between carrier (5) and sensing element (4) to protect the second surface of membra

Abstract: The invention concerns a pressure sensor (1), able to operate at high temperature and measure the pressure of a hostile medium, comprising:

Abstract: The invention concerns a pressure sensor (1), able to operate at high temperature and measure the pressure of a hostile medium, comprising: a sensing element (4) integrating a membrane (8) in monocrystalline silicon carbide, made by micro-machining a substrate in polycrystalline silicon carbide, a first surface of membrane (8) intended to contact said medium, a second surface of membrane (8) comprising membrane deformation detection means (9) connected to electric contacts (10) to connect electric connection means (11), the surfaces of sensing element (4) contacting said medium being chemically inert to this medium; a carrier (5) to support sensing element (4) so that said first surface of membrane (8) may be contacted with said medium and the second surface of membrane (8) may be shielded from said medium, carrier (5) being in polycrystalline silicon carbide; a seal strip (6), in material containing silicon carbide, brazed between carrier (5) and sensing element (4) to protect the second surface of membra

Abstract: The invention concerns a thin layer semi-conductor structure including a semi-conductor surface layer (2) separated from a support substrate (1) by an intermediate zone (3), the intermediate zone (3) being a multi-layer electrically insulating the semi-conductor surface layer from the support substrate. The intermediate zone has a considered sufficiently good electrical quality of interface with the semi-conductor surface layer and includes at least one first layer, of satisfactory thermal conductivity to provide a considered as correct operation of the electronic device or devices which are to be elaborated from the semi-conductor surface layer (2), the intermediate zone including additionally a second insulating layer of low dielectric constant, located between the first layer and the support substrate.

Abstract: A carbon fiber fabric having large specific surface area is made using a rayon precursor, and a catalyst is fixed on the fabric by impregnation or by cationic exchange. The carbon fiber fabric has pores with a mean size lying in the range 0.3 nm to 3 nm, a carbon content greater than 99%, and a high density of functional groups per unit area which favors the dispersion of metal catalyst in the form of fine particles and which is good for highly selective catalytic reactions in fine chemistry.

Abstract: This invention relates to a process for the manufacture of one electronic structure comprising at least one active component and at least one passive component or element on a support substrate made of an insulating material. A characteristic process comprises the following steps: make the active component in a surface layer made of semiconducting material from an initial substrate comprising a wafer of semiconducting material supporting the said surface layer, make electrical insulation areas capable of insulating the passive component or element from the active component, make the passive component or element on and/or in the electrical insulation areas, prepare the surface of the initial substrate face with the said electronic structure to make this face compatible for bonding with another substrate by molecular bonding, perform the bonding, the other substrate being the said support substrate made of an insulating material, eliminate all or part of the wafer of semiconducting material.

Abstract: Process for transfer of a microstructure (12) from an initial substrate (10) to a final substrate (32). The process includes the following steps in sequence:bonding between the initial substrate (10) and an intermediate substrate (24), the microstructure facing the intermediate substrate,formation of at least one layer (30) of bond material on at least one selected region (16) of the initial substrate including the microstructurebring the said selected region (16) into contact with the final substrate,treatment of the bond material in an area corresponding to the selected region (16), to increase the bond force,breaking the selected region (16) of the initial substrate, from the intermediate substrate (24).

Abstract: A process for producing an improved non-volatile storage cell of the metal-ferroelectric-semiconductor type is provided. The non-volatile storage cell has at least one metal-ferroelectric-semiconductor transistor formed in a semiconductor substrate and having a source (5), a drain (6), and a gate (4). The gate is insulated from the source and the drain by a ferroelectric layer (2). The transistor has at least one lateral programming electrode (BL) in contact with the ferroelectric layer and insulated from the gate. In a preferred embodiment the cell also has a dielectric layer (7) interposed between the ferroelectric layer and the substrate. Particular utility for the present invention is found in the area of static memory devices, although other utilities are contemplated.

Abstract: The invention relates to a gaseous phase chemical treatment reactor for wafers. The aim of the invention is to produce a reactor in which only the face of the wafer to be treated is in fact treated. This aim is achieved with the aid of a reactor comprising at least one treatment chamber (19) located within a main chamber (9) and connected by one of its ends to means (17) for injecting a treatment gas onto a wafer (1) and by its other end to a means (15) for securing said wafer, in that the latter is gripped between a heating susceptor or base (13) and the retaining means (15) in such a way as to seal said treatment chamber (19) and maintain within the latter a pressure below that of the main chamber (9). The invention more particularly relates to reactors for depositing tungsten on silicon wafers.