Patents by Inventor Jean-Pierre Oddou

Jean-Pierre Oddou has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230263082
    Abstract: An integrated circuit includes a substrate with an active area, a first insulating layer, a second insulating layer, and a phase-change material. The integrated circuit further includes a heating element in an L-shape, with a long side in direct physical contact with the phase-change material and a short side in direct physical contact with a via. The heating element is surrounded by first, second, and third insulating spacers, with the first insulating spacer having a planar first sidewall in contact with the long side of the heating element, a convex second sidewall, and a planar bottom face in contact with the short side of the heating element. The second and third insulating spacers are in direct contact with the first insulating spacer and the long side of the heating element.
    Type: Application
    Filed: April 3, 2023
    Publication date: August 17, 2023
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck ARNAUD, David GALPIN, Stephane ZOLL, Olivier HINSINGER, Laurent FAVENNEC, Jean-Pierre ODDOU, Lucile BROUSSOUS, Philippe BOIVIN, Olivier WEBER, Philippe BRUN, Pierre MORIN
  • Patent number: 11653582
    Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
    Type: Grant
    Filed: November 8, 2018
    Date of Patent: May 16, 2023
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck Arnaud, David Galpin, Stephane Zoll, Olivier Hinsinger, Laurent Favennec, Jean-Pierre Oddou, Lucile Broussous, Philippe Boivin, Olivier Weber, Philippe Brun, Pierre Morin
  • Publication number: 20190140176
    Abstract: An electronic chip includes memory cells made of a phase-change material and a transistor. First and second vias extend from the transistor through an intermediate insulating layer to a same height. A first metal level including a first interconnection track in contact with the first via is located over the intermediate insulating layer. A heating element for heating the phase-change material is located on the second via, and the phase-change material is located on the heating element. A second metal level including a second interconnection track is located above the phase-change material. A third via extends from the phase-change material to the second interconnection track.
    Type: Application
    Filed: November 8, 2018
    Publication date: May 9, 2019
    Applicants: STMicroelectronics (Crolles 2) SAS, STMicroelectronics (Grenoble 2) SAS, STMicroelectronics (Rousset) SAS
    Inventors: Franck ARNAUD, David GALPIN, Stephane ZOLL, Olivier HINSINGER, Laurent FAVENNEC, Jean-Pierre ODDOU, Lucile BROUSSOUS, Philippe BOIVIN, Olivier WEBER, Philippe BRUN, Pierre MORIN
  • Patent number: 10199413
    Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.
    Type: Grant
    Filed: December 12, 2017
    Date of Patent: February 5, 2019
    Assignees: STMICROELECTRONICS SA, STMICROELECTRONICS(CROLLES 2) SAS
    Inventors: Axel Crocherie, Jean-Pierre Oddou, Stéphane Allegret-Maret, Hugues Leininger
  • Patent number: 10128295
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Grant
    Filed: January 10, 2018
    Date of Patent: November 13, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny
  • Publication number: 20180158861
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Application
    Filed: January 10, 2018
    Publication date: June 7, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny
  • Publication number: 20180102387
    Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.
    Type: Application
    Filed: December 12, 2017
    Publication date: April 12, 2018
    Inventors: Axel Crocherie, Jean-Pierre Oddou, Stéphane Allegret-Maret, Hugues Leininger
  • Publication number: 20180076250
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Application
    Filed: September 13, 2016
    Publication date: March 15, 2018
    Applicant: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny
  • Patent number: 9917126
    Abstract: A semiconductor substrate includes a photodiode region, a charge storage region electrically coupled to the photodiode region and a capacitive deep trench isolation (CDTI) structure including a conductive region positioned between the photodiode region and the charge storage region. A contact etch stop layer overlies the semiconductor substrate and a premetallization dielectric layer overlies the contact etch stop layer. A first trench, filled with a metal material, extends through the premetallization dielectric layer and bottoms out at or in the contact etch stop layer. A second trench, also filled with the metal material, extends through the premetallization dielectric layer and the contact etch stop layer and bottoms out at or in the conductive region of the CDTI structure. The metal filled first trench forms an optical shield between the photodiode region and the charge storage region. The metal filled second trench forms a contact for biasing the CDTI structure.
    Type: Grant
    Filed: September 13, 2016
    Date of Patent: March 13, 2018
    Assignee: STMicroelectronics (Crolles 2) SAS
    Inventors: Sebastien Lagrasta, Delia Ristoiu, Jean-Pierre Oddou, Cécile Jenny
  • Patent number: 9859319
    Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.
    Type: Grant
    Filed: October 27, 2015
    Date of Patent: January 2, 2018
    Assignees: STMicroelectronics SA, STMicroelectronics (Crolles 2) SAS
    Inventors: Axel Crocherie, Jean-Pierre Oddou, Stéphane Allegret-Maret, Hugues Leininger
  • Patent number: 9685475
    Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.
    Type: Grant
    Filed: September 8, 2015
    Date of Patent: June 20, 2017
    Assignee: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
  • Publication number: 20160233258
    Abstract: A color image sensor including an array of pixels is formed in a semiconductor layer having a back side that receives an illumination. Insulated conductive walls penetrate into the semiconductor layer from the back side and separate the pixels from one another. For each pixel, a color pixel penetrates into from 5 to 30% of a thickness of the semiconductor layer from the back side and occupies at least 90% of the surface area delimited by the walls. An electrically-conductive layer extends from the lateral wall of the filter all the way to the walls.
    Type: Application
    Filed: October 27, 2015
    Publication date: August 11, 2016
    Inventors: Axel CROCHERIE, Jean-Pierre ODDOU, Stéphane ALLEGRET-MARET, Hugues LEININGER
  • Publication number: 20160099278
    Abstract: A back-illuminated integrated imaging device is formed from a semiconductor substrate including a zone of pixels bounded by capacitive deep trench isolations. A peripheral zone is located outside the zone of pixels. A continuous electrically conductive layer forms, in the zone of pixels, an electrode in a trench for each capacitive deep trench isolation, and forms, in the peripheral zone, a redistribution layer for electrically coupling the electrode to a biasing contact pad. The electrode is located in the trench between a trench dielectric and at least one material for filling the trench.
    Type: Application
    Filed: September 8, 2015
    Publication date: April 7, 2016
    Applicant: STMICROELECTRONICS (CROLLES 2) SAS
    Inventors: Francois Guyader, Jean-Pierre Oddou, Stephane Allegret-Maret, Mickael Gros-Jean
  • Patent number: 9224775
    Abstract: An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7.
    Type: Grant
    Filed: July 30, 2014
    Date of Patent: December 29, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Pierre Carrere, Patrick Gros D'Aillon, Stephane Allegret-Maret, Jean-Pierre Oddou
  • Patent number: 9099604
    Abstract: A method for manufacturing an image sensor, including the successive steps of: forming columns of a semiconductor material; forming one or several pixels at a first end of each of the columns; and deforming the structure so that the second ends of each of the columns come closer to each other or draw away from each other to form a surface in the shape of a polyhedral cap.
    Type: Grant
    Filed: April 8, 2013
    Date of Patent: August 4, 2015
    Assignees: STMicroelectronics (Crolles 2) SAS, STMicroelectronics S.A.
    Inventors: François Roy, Lucile Broussous, Julien Michelot, Jean-Pierre Oddou
  • Publication number: 20150035106
    Abstract: An integrated circuit includes a back side illuminated image sensor formed by a substrate supporting at least one pixel, an interconnect part situated above a front side of the substrate and an anti-reflective layer situated above a back side of the substrate. The anti-reflective layer may be formed of a silicon nitride layer. An additional layer is situated above the anti-reflective layer. The additional layer is formed of one of amorphous silicon nitride or hydrogenated amorphous silicon nitride, in which the ratio of the number of silicon atoms per cubic centimeter to the number of nitrogen atoms per cubic centimeter is greater than 0.7.
    Type: Application
    Filed: July 30, 2014
    Publication date: February 5, 2015
    Applicants: STMicroelectronics (Crolles 2) SAS, Commissariat A L'Energie Atomique et aux Energies Alternatives
    Inventors: Jean-Pierre Carrere, Patrick Gros D'Aillon, Stephane Allegret-Maret, Jean-Pierre Oddou
  • Patent number: 8610048
    Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
    Type: Grant
    Filed: September 22, 2011
    Date of Patent: December 17, 2013
    Assignee: STMicroelectronics S.A.
    Inventors: Jerome Alieu, Simon Guillaumet, Christophe Legendre, Hughes Leininger, Jean-Pierre Oddou, Marc Vincent
  • Publication number: 20120161269
    Abstract: A front-side illuminated image sensor, including photodetection regions, charge transfer elements, and an interconnection stack, all formed at the surface of a semiconductor substrate, microcavities being formed in the interconnection stack in front of the photodetection regions, microcavities being filled with materials forming color filters including metal pigments, regions of a material forming a barrier against ionic diffusion extending on the lateral walls of the microcavities.
    Type: Application
    Filed: December 22, 2011
    Publication date: June 28, 2012
    Applicants: STMicroelectronics S.A., Commissariat a l`Energie Atomique et aux Energies Alternatives, STMicroelectronics (Crolles 2) SAS
    Inventors: Christophe Aumont, Jean-Pierre Oddou, Jérôme Vaillant, Patrick Gros D'Aillon
  • Publication number: 20120006980
    Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
    Type: Application
    Filed: September 22, 2011
    Publication date: January 12, 2012
    Applicant: STMICROELECTRONICS S.A.
    Inventors: JÉRÔME ALIEU, SIMON GUILLAUMET, CHRISTOPHE LEGENDRE, HUGHES LEININGER, JEAN-PIERRE ODDOU, MARC VINCENT
  • Patent number: 8044443
    Abstract: A method for producing a photosensitive integrated circuit including producing circuit control transistors, producing, above the control transistors, and between at least one upper electrode and at least one lower electrode, at least one photodiode, by amorphous silicon layers into which photons from incident electromagnetic radiation are absorbed, producing at least one passivation layer, between the lower electrode and the control transistors, and producing, between the control transistors and the external surface of the integrated circuit, a reflective layer capable of reflecting photons not absorbed by the amorphous silicon layers.
    Type: Grant
    Filed: November 21, 2006
    Date of Patent: October 25, 2011
    Assignee: STMicroelectronics S.A.
    Inventors: Jérôme Alieu, Simon Guillaumet, Christophe Legendre, Hugues Leininger, Jean-Pierre Oddou, Marc Vincent