Abstract: The invention relates to apparatus for monitoring the operation of electronic equipment having a plurality of circuits to be monitored, each of which has a fault indication terminal (24). In accordance with the invention, fault simulation means comprise a cyclic address counter (9) having a higher number of states than there are circuits to be monitored, and which is arranged to switch the binary fault indicating terminal of a circuit to its fault condition when indicating the address of the circuit. When indicating an address that is not allocated to any of the circuits, none of the circuits ought to respond. A check is thus performed on the operation of the fault simulation means itself. The invention is applicable to electronic equipment requiring a high degree of security in operation, e.g. a redundant time base. The equipment may be analogue or digital.