Patents by Inventor Jean-Robert Clerge

Jean-Robert Clerge has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Open drain driver having enhanced immunity to I/O ground noise
    Patent number: 6472906
    Abstract: An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.
    Type: Grant
    Filed: December 27, 2000
    Date of Patent: October 29, 2002
    Assignees: Sony Corporation, Sony Electronics Inc.
    Inventors: Ikuo Jimmy Sanwo, Mahyar Nejat, Jean-Robert Clerge
  • Open drain driver having enhanced immunity to I/O ground noise
    Publication number: 20020113621
    Abstract: An open drain I/O driver includes an input node, an output node, a first reference node, a first transistor, and noise immunity circuitry. The first transistor has its gate coupled to the input node and its conducting path coupled in series with the output node and the first reference node. The first transistor operates to uncouple the output node from the first reference node in response to an input voltage applied to the input node. The noise immunity circuitry keeps the output node uncoupled from the first reference node during undershoot noise in a first reference voltage that causes the first transistor to change from an off state to an on state. The noise immunity circuitry includes second and third transistors. The second transistor has its gate coupled to the input node and its conducting path coupled in series with the conducting path of the first transistor. The third transistor is configured to keep the second transistor in an off state during the undershoot noise.
    Type: Application
    Filed: December 27, 2000
    Publication date: August 22, 2002
    Applicant: Sony Corporation and Sony Electronics Inc.
    Inventors: Ikuo Jimmy Sanwo, Mahyar Nejat, Jean-Robert Clerge
  • Apparatus and method of providing a four input logic function
    Publication number: 20020089354
    Abstract: The present invention is a method and apparatus for providing a four input logic function.
    Type: Application
    Filed: January 8, 2001
    Publication date: July 11, 2002
    Inventors: Ikuo Jimmy Sanwo, Mahyar Nejat, Jean-Robert Clerge