Patents by Inventor Jean Roggen
Jean Roggen has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
-
Patent number: 6518088Abstract: A structural shape has an injection molded, three-dimensional substrate composed of an electrically insulating polymer, polymer studs planarly arranged on the underside of the substrate and co-formed during injection molding, outside terminals formed on the polymer studs by a solderable end surface, interconnections fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals, and at least one chip arranged on the substrate and whose terminals are electrically conductively connected to the inside terminals. The structural shape is suitable for single, few or multi chip module and unites the advantages of a ball grid array with the advantages of MID technology (Molded Interconnection Devices). The manufacture and metallization of the polymer studs can take place with minimal additional outlay in the framework of the method steps already required in the MID technology.Type: GrantFiled: October 2, 2000Date of Patent: February 11, 2003Assignee: Siemens N.V. and Interuniversitair Micro-Electronica Centrum VZWInventors: Marcel Heerman, Joost Wille, Jozef Puymbroeck Van, Jean Roggen, Eric Beyne, Rita Hoof Van
-
Patent number: 6249048Abstract: A structural shape has an injection molded, three-dimensional substrate composed of an electrically insulating polymer, polymer studs planarly arranged on the underside of the substrate and co-formed during injection molding, outside terminals formed on the polymer studs by a solderable end surface, interconnections fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals, and at least one chip arranged on the substrate and whose terminals are electrically conductively connected to the inside terminals. The structural shape is suitable for single, few or multi chip module and unites the advantages of a ball grid array with the advantages of MID technology (Molded Interconnection Devices). The manufacture and metallization of the polymer studs can take place with minimal additional outlay in the framework of the method steps already required in the MID technology.Type: GrantFiled: June 8, 1999Date of Patent: June 19, 2001Assignees: Siemens N.V., Interuniversitair Micro-ElectronicaInventors: Marcel Heerman, Joost Wille, Jozef Puymbroeck Van, Jean Roggen, Eric Beyne, Rita Hoof Van
-
Patent number: 6130478Abstract: A polymer stud grid array for microwave circuits is proposed which includes an injection-molded, three-dimensional substrate that is fabricated from an electrically insulating polymer. The substrate includes a plurality of polymer studs which are arranged over the underside of the substrate and which are integrally formed with the substrate during the injection-molding process. Signal connections are formed on the studs which include an end surface that is capable of being soldered. Potential connections are formed on at least one of the studs. The potential connection also includes an end surface that is capable of being soldered. Striplines are also constructed which connect the studs to the microwave circuit. Each stripline includes a first structured metal layer disposed on the underside of the substrate, a dielectric layer disposed on the first metal layer and a second structured metal layer disposed on top of the dielectric layer.Type: GrantFiled: April 18, 1998Date of Patent: October 10, 2000Assignees: Siemens N.V., Interuniversitair Micro-Electronica-Centrum VZWInventors: Ann Dumoulin, Marcel Heerman, Jean Roggen, Eric Beyne, Rita van Hoof
-
Patent number: 6122172Abstract: In order to achieve better dissipation of the heat losses, a polymer stud grid array in proposed havingan injection-molded, three-dimensional substrate (S) composed of an electrically insulating polymer,polymer studs (PS) which are arranged over the area on the underneath of the substrate (S) and are integrally formed during injection molding,external connections which are formed on the polymer studs (PS) by an end surface which can be soldered,conductor runs which are formed at least on the underneath of the substrate (S) and connect the external connections to internal connections,at least one heat sink (WL) which is partially coated during the injection molding of the substrate (S), and havingat least one chip or wiring element (VE) which is arranged on the heat sink (WL) and whose connections are electrically conductively connected to the internal connections.The new configuration is suitable in particular for power components or power modules in a polymer stud grid array package.Type: GrantFiled: April 16, 1998Date of Patent: September 19, 2000Assignees: Siemens NV, Interuniversitair Micro-Electronica-Centrum VZWInventors: Ann Dumoulin, Marcel Heerman, Jean Roggen, Eric Beyne, Rita van Hoof
-
Patent number: 5929516Abstract: A structural shape has an injection molded, three-dimensional substrate composed of an electrically insulating polymer, polymer studs planarly arranged on the underside of the substrate and co-formed during injection molding, outside terminals formed on the polymer studs by a solderable end surface, interconnections fashioned at least on the underside of the substrate that connect the outside terminals to inside terminals, and at least one chip arranged on the substrate and whose terminals are electrically conductively connected to the inside terminals. The structural shape is suitable for single, few or multi chip module and unites the advantages of a ball grid array with the advantages of MID technology (Molded Interconnection Devices). The manufacture and metallization of the polymer studs can take place with minimal additional outlay in the framework of the method steps already required in the MID technology.Type: GrantFiled: March 21, 1997Date of Patent: July 27, 1999Assignees: Siemens N.V., Interuniversitair Micro-Electronica Centrum VZWInventors: Marcel Heerman, Joost Wille, Jozef Van Puymbroeck, Jean Roggen, Eric Beyne, Rita Van Hoof
-
Patent number: 5915838Abstract: An apparatus and method for measuring a parameter of a sample or component at a measurement temperature, wherein the parameter and the measurement temperature are measured at substantially the same time. A temperature coefficient of the sample or component is also established by using temperature fluctuations measured at or near the sample at the time at which the parameter is measured. The temperature coefficient is used to correct the measured parameter data and enhance its stability.Type: GrantFiled: May 19, 1998Date of Patent: June 29, 1999Assignees: IMEC vzw, Limburgs Universitaire CampusInventors: Lambert Stals, Luc De Schepper, Jean Roggen, Ward De Ceuninck
-
Patent number: 5833365Abstract: An apparatus and method for measuring a parameter of a sample or component at a measurement temperature, wherein the parameter and the measurement temperature are measured at substantially the same time. A temperature coefficient of the sample or component is also established by using temperature fluctuations measured at or near the sample at the time at which the parameter is measured. The temperature coefficient is used to correct the measured parameter data and enhance its stability.Type: GrantFiled: March 22, 1996Date of Patent: November 10, 1998Assignees: Interuniversitair Micro-Electronika Centrum vzw, Limburgs Universitair CentrumInventors: Lambert Stals, Luc De Schepper, Jean Roggen, Ward De Ceuninck