Abstract: A data processing apparatus comprises processing circuitry to execute processing instructions, the processing circuitry comprising: a set of physical registers; instruction decoder circuitry to decode processing instructions; detector circuitry to detect groups of instructions which comply with a conflict condition, in which a group of instructions complies with the conflict condition at least when a given storage element is written to by a maximum of one instruction of that group of instructions; instruction issue circuitry to issue decoded instructions for execution; and instruction execution circuitry to execute instructions decoded by the instruction decoder circuitry.

Abstract: A method for triggering prefetching of memory address translations for memory access requests to be issued by a memory access component of a processor in a data processing system to a memory management function in the data processing system is provided. The method includes obtaining command data from one or more memory access commands in a sequence of memory access commands for the memory access component, predicting one or more memory addresses, for which one or more memory address translations are likely to be required by the memory management function to process one or more memory access requests, from the obtained command data, in response to the predicting, performing one or more trigger operations to trigger a prefetch of the one or more memory address translations, using the predicted one or more memory addresses, in advance of the one or more memory access requests.

Abstract: The invention relates to a transistorized static relay.This relay comprises a power amplifier stage having a first bipolar transistor of a first type (npn or pnp), whose collector is connected to the input of the relay and whose emitter is connected to the output of said relay, or vice versa. This relay also has a control stage of the power stage transistor. This control stage comprises at least one bipolar control transistor of a second type (pnp or npn) opposite to the first type, whose emitter is connected to the input or output and whose collector is connected to the base of the transistor of the power stage. The base of the control transistor receives a switching control current interrupting or authorizing the flow of supply current in the load connected to the output of the relay, the impedance of the amplifier stage varying in the reverse direction of the value of the control current and the collector of the low value power transistor is connected to the generator supplying the relay by an impedance.

Abstract: The invention relates to a relay authorizing or interrupting the flow of a current in a load circuit.This relay comprises a static electronic switch connected to the load circuit, a control circuit connected to the switch for authorizing or interrupting the flow of current in the load circuit due to the switch. The control circuit comprises a supply input connected to one point of the load circuit and, connected in series between said input and the load circuit, a control switch, a current generator with two terminals and at least one impedance limiting the current flowing in the load circuit to a negligible value compared with the value of the current flowing in the load circuit when said flow is permitted. The voltage at the terminals of the generator is at least equal to the highest voltage between two random points of the load circuit.Application to circuits in which flows a current with a random direction or an alternating current, or to a current inverter.