Patents by Inventor Jean Stephane
Jean Stephane has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 11969848Abstract: The tool includes a base including a rigid carrier and a flexible collar encircling the rigid carrier; an elastically compressible interface; and a flexible buffer including a central portion that is located in line with the rigid carrier and a peripheral portion that is located transversely therebeyond. This peripheral portion is connected to the carrier exclusively via the interface and via the collar, wherein the collar is configured so that the tool is elastically deformable between a rest position that it adopts in the absence of stress and a reference position in which the transverse end second surface of the flexible buffer is pressed against a reference surface that is spherical and of radius included between 40 mm and 1500 mm.Type: GrantFiled: October 27, 2017Date of Patent: April 30, 2024Assignee: Essilor InternationalInventors: Eric Gacoin, Pierre Kress, Jean Stephane, Jonathan Saulny
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Publication number: 20230295181Abstract: Provided herein are compounds that modulate the activity of melanoma inhibitor of apoptosis (ML-IAP) protein, compositions comprising the compounds, and methods of using the compounds and compositions comprising the compounds.Type: ApplicationFiled: April 29, 2021Publication date: September 21, 2023Inventors: Nicholas David Peter COSFORD, Dominik HEIMANN, Peter TERIETE, Sumit Kumar CHANDA, Lars PACHE, Laurent Jean Stephane DE BACKER, Nicole BATA
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Publication number: 20230176400Abstract: Disclosed is a method implemented by a computer for determining surfacing data to obtain a surface of a lens element, the surface of the lens element including: a refraction area having a first curvature; and multiple optical elements placed on at least part of the finished optical surface, each optical element having at least a second curvature.Type: ApplicationFiled: April 21, 2021Publication date: June 8, 2023Inventors: Eric GACOIN, Khamphone SISAVANH, Jean STEPHANE
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Patent number: 11320526Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).Type: GrantFiled: June 20, 2019Date of Patent: May 3, 2022Assignee: NXP USA, Inc.Inventors: Didier Salle, Cristian Pavao Moreira, Dominique Delbecq, Olivier Doaré, Jean-Stephane Vigier, Birama Goumballa
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Publication number: 20220016546Abstract: A method for continuous exchange of material includes countercurrent contacting of a first fluid phase and a second fluid phase that are not completely miscible. The contacting is carried out in a single centrifugal partition chromatography (CPC) apparatus into which only the first and second fluid phases introduced. The apparatus includes a plurality of cells, each with a stationary phase immobilized and a mobile phase passing through the stationary phase. The following steps are carried out successively: a) the mobile phase is formed by the first fluid phase, and the stationary phase immobilized in the cells is formed by the second fluid phase; b) the mobile phase is formed by the second fluid phase, and the stationary phase immobilized in the cells is formed by the first fluid phase; c) repetition of the succession of steps a) and b) each step being carried out immediately after the preceding step.Type: ApplicationFiled: November 14, 2019Publication date: January 20, 2022Inventors: Jean-Stéphane CONDORET, Philippe DESTRAC, Christophe GOURDON, Jack LEGRAND, Luc MARCHAL
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Patent number: 11143746Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.Type: GrantFiled: August 17, 2018Date of Patent: October 12, 2021Assignee: NXP USA, Inc.Inventors: Jean-Stéphane Vigier, Dominique Delbecq, Cristian Pavao-Moreira, Andres Barrilado-Gonzalez
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Publication number: 20210302535Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.Type: ApplicationFiled: August 17, 2018Publication date: September 30, 2021Inventors: Jean-Stéphane VIGIER, Dominique DELBECQ, Cristian PAVAO-MOREIRA, Andres BARRILADO-GONZALEZ
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Patent number: 11131763Abstract: A fast chirp Phase Locked Loop with a phase preset includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A phase preset circuit connects to the digital controller and the filter. The phase preset circuit supplies a phase preset current during a start frequency time preceding the chirp phase. The phase preset current is proportional to a VCO gain of the VCO and inversely proportional to a chirp current during the chirp phase.Type: GrantFiled: May 30, 2019Date of Patent: September 28, 2021Assignee: NXP USA, INC.Inventors: Jean-Stephane Vigier, Didier Salle, Cristian Pavao-Moreira, Julien Orlando
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Patent number: 11131762Abstract: A fast chirp Phase Locked Loop with a boosted return time includes a Voltage Controlled Oscillator, VCO, generating a Frequency Modulated Continuous Waveform, FMCW. The VCO responds to a filtered output voltage of a filter connected to a charge pump. A digital controller modifies the FMCW to generate a chirp phase and a return phase. The chirp phase includes a first linear change of the FMCW from a start frequency to a stop frequency. The return phase includes a second linear change of the FMCW from the stop frequency to the start frequency. A boost circuit connects to the digital controller and the filter. The boost circuit supplies a boost current during the return phase. The boost current is proportional to a return slope of the return phase and inversely proportional to a VCO gain of the VCO.Type: GrantFiled: May 30, 2019Date of Patent: September 28, 2021Assignee: NXP USA, INC.Inventors: Jean-Stephane Vigier, Didier Salle, Cristian Pavao-Moreira, Julien Orlando
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Patent number: 11054513Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).Type: GrantFiled: June 21, 2019Date of Patent: July 6, 2021Assignee: NXP USA, INC.Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
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Patent number: 10700672Abstract: An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold.Type: GrantFiled: October 3, 2019Date of Patent: June 30, 2020Assignee: NXP USA, Inc.Inventors: Pierre Savary, Cristian Pavao Moreira, Matthis Bouchayer, Jean-Stephane Vigier
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Patent number: 10644872Abstract: A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one of at least one master device and at least one slave device comprises a demodulator circuit (564, 565) configured to: receive a modulated embedded master-slave clock signal (584) that comprises a system clock signal (582) with an embedded frame start signal (580); demodulate the modulated embedded master-slave clock signal (584); and re-create therefrom the system clock signal (588, 585) and the frame start signal (590, 586).Type: GrantFiled: June 21, 2019Date of Patent: May 5, 2020Assignee: NXP USA, INC.Inventors: Cristian Pavao Moreira, Birama Goumballa, Jean-Stephane Vigier, Matthis Bouchayer
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Publication number: 20200136599Abstract: An electronic system includes a clock generation circuit to generate a clock signal; and a duty cycle monitoring circuit, DTC, to monitor a duty cycle of the generated clock signal. The DTC includes a differential signal generator circuit to generate an inverted and a non-inverted representation of the generated clock signal. An averaging circuit averages the non-inverted representation and the inverted representation of the generated clock signal. A comparison circuit includes at least a first comparator to compare the averaged non-inverted representation of the generated clock signal with a second respective reference voltage threshold and a second comparator configured to compare the averaged inverted representation with a first respective reference voltage threshold.Type: ApplicationFiled: October 3, 2019Publication date: April 30, 2020Inventors: Pierre SAVARY, Cristian Pavao Moreira, Matthis Bouchayer, Jean-Stephane Vigier
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Patent number: 10615958Abstract: A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).Type: GrantFiled: June 20, 2019Date of Patent: April 7, 2020Assignee: NXP USA, INC.Inventors: Jean-Stephane Vigier, Cristian Pavao Moreira, Matthis Bouchayer
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Publication number: 20200057140Abstract: A chirp linearity detector, integrated circuit, and method are provided. The chirp linearity detector comprises a phase-locked loop (PLL) frequency sampling circuit and a frequency sweep linearity measuring circuit. The PLL frequency sampling circuit comprises a frequency divider circuit for receiving a PLL output signal from a PLL and for providing a frequency divided output signal, a first low pass filter circuit for receiving the frequency divided output signal, for reducing harmonic mixing, and for providing a mixer input signal, a mixer circuit for receiving the mixer input signal, for mixing the mixer input signal with a local oscillator signal, and for providing a mixer output signal, a second low pass filter circuit for performing anti-aliasing filtering and for providing an analog-to-digital converter (ADC) input signal, and an ADC circuit for digitizing the ADC input signal and for providing a digital output signal.Type: ApplicationFiled: August 17, 2018Publication date: February 20, 2020Inventors: Jean-Stephane Vigier, Dominique Delbecq, Cristian Pavao Moreira, Andres Barrilado Gonzalez
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Publication number: 20200003882Abstract: A communication unit (300) is described that includes a plurality of cascaded devices that includes at least one master device and at least one slave device configured in a master-slave arrangement. The at least one master device comprises a modulator circuit (362) configured to: receive a system clock signal and a frame start signal; modulate the system clock signal with the frame start signal to produce a modulated master-slave clock signal (384); and transmit the modulated master-slave clock signal (384) to the at least one slave device. The at least one slave device comprises a demodulator circuit (364) configured to: receive and demodulate the modulated master-slave clock signal (384); and re-create therefrom the system clock signal (388, 385) and the frame start signal (390, 386).Type: ApplicationFiled: June 20, 2019Publication date: January 2, 2020Inventors: Didier Salle, Cristian Pavao Moreira, Dominique Delbecq, Olivier Doaré, Jean-Stephane Vigier, Birama Goumballa
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Publication number: 20200007310Abstract: A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one of at least one master device and at least one slave device comprises a demodulator circuit (564, 565) configured to: receive a modulated embedded master-slave clock signal (584) that comprises a system clock signal (582) with an embedded frame start signal (580); demodulate the modulated embedded master-slave clock signal (584); and re-create therefrom the system clock signal (588, 585) and the frame start signal (590, 586).Type: ApplicationFiled: June 21, 2019Publication date: January 2, 2020Inventors: Cristian Pavao Moreira, Birama Goumballa, Jean-Stephane Vigier, Matthis Bouchayer
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Publication number: 20200003883Abstract: A communication unit (700) is described that includes a plurality of cascaded devices that comprise at least one master device (710) and at least one slave device (720, 723) configured in a master-slave arrangement. The at least one master device (710) and at least one slave device (720, 723) each comprise: an analog-to-digital converter, ADC, (741, 742) configured to use a same re-created system clock signal (788, 790) to align respective sampling instants between each ADC (741, 742). The at least one master device (710) comprises: a clock generation circuit comprising an internally-generated reference phase locked loop circuit (708), configured to output a system clock signal (782, 784); and a modulator circuit (762) coupled to the clock generation circuit and configured to receive and distribute the system clock signal (784).Type: ApplicationFiled: June 21, 2019Publication date: January 2, 2020Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
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Publication number: 20200003862Abstract: A communication unit (900) includes a plurality of cascaded devices that comprise at least one master device (910) and at least one slave device (920, 923) configured in a master-slave arrangement. The at least one master device (910) and at least one slave device (920, 923) each include: a demodulator circuit (964, 965) configured to receive a distributed reference clock signal (984) and re-create a system clock signal (988, 990) therefrom; a clock generation circuit comprising an internally-generated reference phase locked loop configured to receive the re-created system clock signal (988, 990) to create a master-slave clock signal; and an analog-to-digital converter, ADC, (941, 942) coupled to the reference phase locked loop and configured to use a same master-slave clock signal (988, 990) to align respective sampling instants between each ADC (941, 942) of the at least one master device (910) and at least one slave device (920, 923).Type: ApplicationFiled: June 21, 2019Publication date: January 2, 2020Inventors: Olivier Doaré, Didier Salle, Cristian Pavao Moreira, Julien Orlando, Jean-Stephane Vigier, Andres Barrilado Gonzalez
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Publication number: 20200007309Abstract: A communication unit (400, 500) is described that includes a plurality of cascaded devices that comprise at least one master device and at least one slave device configured in a master-slave arrangement and configured to process at least one of: transmit signals, and receive signals. The at least one master device includes: a clock generation circuit configured to output a system clock signal; a modulator circuit (562) coupled to the clock generation circuit and configured to receive the system clock signal and a frame start signal and embed the frame start signal into the system clock signal to produce a modulated embedded master-slave clock signal (584); and transmit the modulated embedded master-slave clock signal (584) to the at least one slave device to synchronise the system clock signal and the frame start signal between the at least one master device (510) and at least one slave device (520).Type: ApplicationFiled: June 20, 2019Publication date: January 2, 2020Inventors: Jean-Stephane Vigier, Cristian Pavao Moreira, Matthis Bouchayer