Patents by Inventor Jean Wu

Jean Wu has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 10461176
    Abstract: A finFET device having a substrate and a fin disposed on the substrate. The fin includes a passive region, a stem region overlying the passive region, and an active region overlying the stem region. The stem region has a first width and the active region has a second width. The first width is less than the second width. The stem region and the active region also have different compositions. A gate structure is disposed on the active region.
    Type: Grant
    Filed: August 14, 2017
    Date of Patent: October 29, 2019
    Assignee: TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
    Inventors: Jean-Pierre Colinge, Kuo-Cheng Ching, Zhiqiang Wu
  • Publication number: 20190319035
    Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.
    Type: Application
    Filed: April 10, 2019
    Publication date: October 17, 2019
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen LIN, Yi-Ching Jean Wu
  • Patent number: 10427225
    Abstract: A cutting insert having two opposing end surfaces, two identical opposing major side surfaces and two identical opposing minor side surfaces. Each end surface has four corners with two lowered corners and two raised corners, the two lowered corners being diagonally opposite each other, the two raised corners being diagonally opposite each other. The cutting insert also includes a major cutting edge formed at an intersection of each major edge and the end surface. A first section of the major cutting edge proximate the raised corner constitutes a leading end of the major cutting edge, and a second section of the major cutting edge proximate the lowered corner constitutes a trailing end of the major cutting edge. An angled margin only partially extends along the leading end of the major cutting edge and segments the major cutting edge.
    Type: Grant
    Filed: November 15, 2017
    Date of Patent: October 1, 2019
    Assignee: KENNAMETAL INC.
    Inventors: Lance David Brunetto, Jean Luc Dufour, Andreas Lieber, Xiangdong Fang, Qiang Wu
  • Patent number: 10421755
    Abstract: The present invention relates to salts of (R)-3-(6-(4-methylphenyl)-pyridin-3-yloxy)-1-aza-bicyclo[2.2.2]octane, to methods for making them or their precursors, to pharmaceutical compositions comprising them, and to their use as medicaments.
    Type: Grant
    Filed: September 22, 2017
    Date of Patent: September 24, 2019
    Assignee: Novartis AG
    Inventors: Wolfgang Marterer, Mahavir Prashad, Edwin Bernard Villhauer, Liladhar Murlidhar Waykole, James Anthony Vivelo, Bertrand Sutter, Jean-Claude Bianchi, Raeann Wu, Denis Har, Piotr H. Karpinski, Massimo Pignone, Doris Stingelin, Eckart Buerger
  • Patent number: 10317019
    Abstract: An illumination device including an LED mounting platform (2) having a peripheral region (2a) and a relatively inner region (2b); at least one warm white LED (3) and at least one cool white LED (4) mounted adjacent the peripheral region (2a) of the LED mounting platform (2), and, at least one RGB LED (5) mounted adjacent the relatively inner region (2b) of the LED mounting platform (2); a diffusion cover (10) configured to allow light emitted from the at least one warm white LED (3), the at least one cool white LED (4), and the at least one RGB LED (5) to pass therethrough; and wherein at least one light emission characteristic of light emitted from the at least one warm white LED (3), the at least one cool white LED (4), and/or the at least one RGB LED (5) is configured to be selectably varied in response to an input control signal so as to produce a plurality of lighting modes.
    Type: Grant
    Filed: August 22, 2014
    Date of Patent: June 11, 2019
    Assignee: TAOLIGHT COMPANY LIMITED
    Inventors: Huahui Li, Jiezhao Wang, Yingying Zhao, Bertrand Delalande, Bruno Couthouis, Jean-Eudes Leroy, Libo Wu
  • Patent number: 10297606
    Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.
    Type: Grant
    Filed: January 11, 2017
    Date of Patent: May 21, 2019
    Assignee: Cypress Semiconductor Corporation
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
  • Publication number: 20190143424
    Abstract: A cutting insert having two opposing end surfaces, two identical opposing major side surfaces and two identical opposing minor side surfaces. Each end surface has four corners comprising two lowered corners and two raised corners, the two lowered corners being diagonally opposite each other, the two raised corners being diagonally opposite each other. The cutting insert also includes a major cutting edge formed at an intersection of each major edge and the end surface. A section of the major cutting edge proximate the raised corner constitutes a leading end of the major cutting edge, and a section of the major cutting edge proximate the lowered corner constitutes a trailing end of the major cutting edge. An angled margin only partially extends along the leading end of the major cutting edge and segments the major cutting edge.
    Type: Application
    Filed: November 15, 2017
    Publication date: May 16, 2019
    Applicant: Kennametal Inc.
    Inventors: Lance David Brunetto, Jean Luc Dufour, Andreas Lieber, Xiangdong Fang, Qiang Wu
  • Patent number: 10162394
    Abstract: Embodiments of a sustainable self-cooling framework for processors using thermoelectric generators that power an arrangement of thermoelectric coolers to reduce the temperature of thermal hot spots generated by a processor are disclosed.
    Type: Grant
    Filed: September 10, 2015
    Date of Patent: December 25, 2018
    Assignee: Arizona Board of Regents on Behalf of Arizona State University
    Inventors: Carole-Jean Wu, Patrick Phelan, Soochan Lee
  • Publication number: 20170170187
    Abstract: A memory device is described. Generally, the device includes a string of memory transistors, a source select transistor coupled to a first end of the string of memory transistor and a drain select transistor coupled to a second end of the string of memory transistor. Each memory transistor includes a gate electrode formed adjacent to a charge trapping layer and there is neither a source nor a drain junction between adjacent pairs of memory transistors or between the memory transistors and source select transistor or drain select transistor. In one embodiment, the memory transistors are spaced apart from adjacent memory transistors and the source select transistor and drain select transistor, such that channels are formed therebetween based on a gate fringing effect associated with the memory transistors. Other embodiments are also described.
    Type: Application
    Filed: January 11, 2017
    Publication date: June 15, 2017
    Applicant: Cypress Semiconductor Corporation
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen LIN, Yi-Ching Jean Wu
  • Patent number: 9570458
    Abstract: Methods and structures for forming semiconductor channels based on gate fringing effect are disclosed. In one embodiment, a NAND flash memory device comprises multiple NAND strings of memory transistors. Each memory transistor includes a charge trapping layer and a gate electrode formed on the charge trapping layer. The memory transistors are formed close to each other to form a channel between an adjacent pair of the memory transistors based on a gate fringing effect associated with the adjacent pair of the memory transistors.
    Type: Grant
    Filed: February 12, 2014
    Date of Patent: February 14, 2017
    Assignee: Cypress Semiconductor Corporation
    Inventors: Youseok Suh, Sung-Yong Chung, Ya-Fen Lin, Yi-Ching Jean Wu
  • Publication number: 20160070318
    Abstract: Embodiments of a sustainable self-cooling framework for processors using thermoelectric generators that power an arrangement of thermoelectric coolers to reduce the temperature of thermal hot spots generated by a processor are disclosed.
    Type: Application
    Filed: September 10, 2015
    Publication date: March 10, 2016
    Inventors: CAROLE-JEAN WU, Patrick Phelan, Soochan Lee
  • Patent number: 9262327
    Abstract: An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
    Type: Grant
    Filed: June 29, 2012
    Date of Patent: February 16, 2016
    Assignee: Intel Corporation
    Inventors: Simon C. Steely, Jr., William C. Hasenplaugh, Aamer Jaleel, Joel S. Emer, Carole-Jean Wu
  • Publication number: 20140006717
    Abstract: An apparatus may comprise a cache file having a plurality of cache lines and a hit predictor. The hit predictor may contain a table of counter values indexed with signatures that are associated with the plurality of cache lines. The apparatus may fill cache lines into the cache file with either low or high priority. Low priority lines may be chosen to be replaced by a replacement algorithm before high priority lines. In this way, the cache naturally may contain more high priority lines than low priority ones. This priority filling process may improve the performance of most replacement schemes including the best known schemes which are already doing better than LRU.
    Type: Application
    Filed: June 29, 2012
    Publication date: January 2, 2014
    Applicant: INTEL CORPORATION
    Inventors: Simon C. STEELY, JR., William C. HASENPLAUGH, Aamer JALEEL, Joel S. EMER, Carole-Jean WU
  • Patent number: 7916523
    Abstract: In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: March 29, 2011
    Assignee: Spansion LLC
    Inventors: An Chen, Sameer Haddad, Yi-Ching Jean Wu, Swaroop Kaza
  • Patent number: 7894243
    Abstract: In a first method of writing data to a resistive memory device (i.e. programming or erasing), successive electrical potentials are applied across the resistive memory device, wherein the successive electrical potentials are of increasing duration. In another method of writing data to a resistive memory device (i.e. programming or erasing), an electrical potential is applied across the resistive memory device, and the level of current through the memory device is sensed as the electrical potential is applied. The application of the electrical potential is ended based on a selected level of current through the resistive memory device.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: February 22, 2011
    Assignee: Spansion LLC
    Inventors: Michael VanBuskirk, Wei Daisy Cai, Colin S. Bill, Yi-Ching Jean Wu
  • Patent number: 7570887
    Abstract: Optical network interface systems and devices are described.
    Type: Grant
    Filed: March 25, 2004
    Date of Patent: August 4, 2009
    Assignee: Lockheed Martin Corporation
    Inventors: Thomas J. Rohrer, Michael Gregory Abernathy, Wilber Andrew Williams, Jean Wu
  • Patent number: 7474579
    Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
    Type: Grant
    Filed: December 20, 2006
    Date of Patent: January 6, 2009
    Assignee: Spansion LLC
    Inventors: Colin S. Bill, Swaroop Kaza, Wei Daisy Cai, Tzu-Ning Fang, David Gaun, Eugen Gershon, Michael A. Van Buskirk, Jean Wu
  • Publication number: 20080151669
    Abstract: Systems and methods are disclosed that facilitate extending data retention time in a data retention device, such as a nanoscale resistive memory cell array, via assessing a resistance level in a tracking element associated with the memory array and refreshing the memory array upon a determination that the resistance of the tracking element has reached or exceeded a predetermined reference threshold resistance value. The tracking element can be a memory cell within the array itself and can have an initial resistance value that is substantially higher than an initial resistance value for a programmed memory cell in the array, such that resistance increase in the tracking cell will cause the tracking cell to reach the threshold value and trigger refresh of the array before data corruption/loss occurs in the core memory cells.
    Type: Application
    Filed: December 20, 2006
    Publication date: June 26, 2008
    Applicant: SPANSION LLC
    Inventors: Colin S. Bill, Swaroop Kaza, Wei Daisy Cai, Tzu-Ning Fang, David Gaun, Eugen Gershon, Michael A. Van Buskirk, Jean Wu
  • Patent number: 7384800
    Abstract: In the method of fabricating a metal-insulator-metal (MIM) device, a first electrode of ?-Ta is provided. The Ta of the first electrode is oxidized to form a Ta2O5 layer on the first electrode. A second electrode of ?-Ta is provided on the Ta2O5 layer. Such a device exhibits strong data retention, along with resistance to performance degradation under high temperatures.
    Type: Grant
    Filed: December 5, 2006
    Date of Patent: June 10, 2008
    Assignee: Spansion LLC
    Inventors: Steven Avanzino, Sameer Haddad, An Chen, Yi-Ching Jean Wu, Suzette K. Pangrle, Jeffrey A. Shields
  • Publication number: 20080130392
    Abstract: In a first method of erasing a resistive memory device, an electrical potential is applied to the gate of a transistor in series with the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials across the resistive memory device. In a second method of erasing a resistive memory device, an electrical potential is applied across the resistive memory device, and successive increasing currents are provided through the resistive memory device by means of providing successive increasing electrical potentials to the gate of a transistor in series with the resistive memory device.
    Type: Application
    Filed: December 5, 2006
    Publication date: June 5, 2008
    Inventors: An Chen, Sameer Haddad, Yi-Ching Jean Wu, Swaroop Kaza