Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.

Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.

Abstract: Examples pertaining to improvement on user equipment (UE) uplink latency in wireless communications are described. When an apparatus is in a special mode, a processor of the apparatus transmits to a network a request for permission to perform an uplink (UL) transmission for a plurality of times. The processor then receives from the network a grant. In response to receiving the grant, the processor performs the UL transmission to the network. In transmitting the request for the plurality of times, the processor transmits the request for the plurality of times at a frequency higher than a frequency at which the request to perform UL transmissions is transmitted to the network when the apparatus is in a normal operational mode.

Abstract: Systems and methods for protecting the privacy of users by controlling access to the users' data. In particular, some embodiments provide for a higher-level declarative language for expressing privacy policies which can be verified using a computer-aided verification tool. The verification tool uses the expressed privacy policies along with language-level assumptions and assertions in the verification process. For example, high-level models of the privacy policies can be reduced to a simpler verification representation (e.g., a Boolean representation) based on a set of assertions. This verification representation can then be submitted to a constraint solver (e.g., Satisfiability Modulo Theories solver) for verification.

Abstract: A resistive memory device is disclosed. The memory device comprises one or more metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation.

Abstract: A method of manufacturing a solar electrode comprising steps of:(a) stencil printing a conductive paste onto a front side of a semiconductor substrate through a printing mask comprising: (i) 60 wt % to 95 wt % of a conductive powder, (ii) 0.1 wt % to 10 wt % of glass frit, (iii) 3 wt % to 30 wt % of an organic medium, (iv) 0.4 wt % to 1.7 wt % of an amide compound, based on the total weight of the conductive paste and (b) firing the applied conductive paste to form an electrode.

Abstract: Systems and methods for protecting the privacy of users by controlling access to the users' data. In particular, some embodiments provide for a higher-level declarative language for expressing privacy policies which can be verified using a computer-aided verification tool. The verification tool uses the expressed privacy policies along with language-level assumptions and assertions in the verification process. For example, high-level models of the privacy policies can be reduced to a simpler verification representation (e.g., a Boolean representation) based on a set of assertions. This verification representation can then be submitted to a constraint solver (e.g., Satisfiability Modulo Theories solver) for verification.

Abstract: Systems and methods for protecting the privacy of users by controlling access to the users' data. In particular, some embodiments provide for a higher-level declarative language for expressing privacy policies which can be verified using a computer-aided verification tool. The verification tool uses the expressed privacy policies along with language-level assumptions and assertions in the verification process. For example, high-level models of the privacy policies can be reduced to a simpler verification representation (e.g., a Boolean representation) based on a set of assertions. This verification representation can then be submitted to a constraint solver (e.g., Satisfiability Modulo Theories solver) for verification.

Abstract: A method of manufacturing a solar electrode comprising steps of:(a) stencil printing a conductive paste onto a front side of a semiconductor substrate through a printing mask comprising: (i) 60 wt % to 95 wt % of a conductive powder, (ii) 0.1 wt % to 10 wt % of glass frit, (iii) 3 wt % to 30 wt % of an organic medium, (iv) 0.4 wt % to 1.7 wt % of an amide compound, based on the total weight of the conductive paste and (b) firing the applied conductive paste to form an electrode.

Abstract: A method of manufacturing a solar electrode comprising steps of: (a) stencil printing a conductive paste onto a front side of a semiconductor substrate through a printing mask comprising, (i) 60 wt % to 95 wt % of a conductive powder, (ii) 0.1 wt % to 10 wt % of glass frit, (iii) 3 wt % to 30 wt % of an organic medium, (iv) 0.4 wt % to 1.7 wt % of polyamide, based on the total weight of the conductive paste and (b) firing the applied conductive paste to form an electrode.

Abstract: Systems and methods for protecting the privacy of users by controlling access to the users' data. In particular, some embodiments provide for a higher-level declarative language for expressing privacy policies which can be verified using a computer-aided verification tool. The verification tool uses the expressed privacy policies along with language-level assumptions and assertions in the verification process. For example, high-level models of the privacy policies can be reduced to a simpler verification representation (e.g., a Boolean representation) based on a set of assertions. This verification representation can then be submitted to a constraint solver (e.g., Satisfiability Modulo Theories solver) for verification.

Abstract: A resistive memory device is disclosed. The resistive memory device comprises one or more metal oxide layers. The resistive memory device displays a property of asymmetric hysteresis loop formation when positive and negative electrical biases are applied across the device.

Abstract: A zinc finger-like peptide for treating cancer, a pharmaceutical composition containing the zinc finger-like peptide and a method for treating cancer are disclosed. In the present invention, the zinc finger-like peptide for treating cancer comprises: at least seven amino acids, wherein the sequence of the at least seven amino acids has 85-100% similarity to a sequence represented by SEQ ID NO: 1.

Abstract: A resistive memory device is disclosed. The memory device comprises one or mo re metal oxide layers. An oxygen vacancy or ion concentrations of the one or more metal oxide layer is controlled in the formation and the operation of the memory device to provide robust memory operation.

Abstract: A resistive memory device is provided that includes a barrier layer in between two metal oxide layers. The barrier layer prevents free flow of oxygen ions between the two metal oxide layers in order to increase the retention period for the data stored in the memory device.

Abstract: A semiconductor device includes a substrate and a memory cell formed on the substrate. The memory cell includes a word line. The semiconductor device also includes a protection area formed in the substrate, a conductive structure configured to extend the word line to the protection area, and a contact configured to short the word line and the protection area.

Abstract: An “Automated, Static Safety Verifier” uses typed assembly language (TAL) and Hoare logic to achieve highly automated, static verification of type and memory safety of an operating system (OS). Various techniques and tools mechanically verify the safety of every assembly language instruction in the OS, run-time system, drivers, and applications, except the boot loader (which can be separately verified). The OS includes a “Nucleus” for accessing hardware and memory, a kernel that builds services running on the Nucleus, and applications that run on top of the kernel. The Nucleus, written in verified assembly language, implements allocation, garbage collection, multiple stacks, interrupt handling, and device access. The kernel, written in C# and compiled to TAL, builds higher-level services, such as preemptive threads, on top of the Nucleus. A Hoare-style verifier with automated theorem prover verifies safety and correctness of the Nucleus. A TAL checker verifies safety of the kernel and applications.

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.

Abstract: A semiconductor fabrication system and method are presented. A three dimensional multilayer integrated circuit fabrication method can include forming a first device layer and forming a second device layer on top of the first device layer with minimal detrimental heat transfer to the first layer by utilizing a controlled laser layer formation annealing process. A controlled laser crystallization process can be utilized and the controlled laser can include creating an amorphous layer; defining a crystallization area in the amorphous layer, where in the crystallization area is defined to promote single crystal growth (i.e. prevent multi-crystalline growth); and applying laser to the crystallization area, wherein the laser is applied in a manner that prevents undesired heat transfer to another layer.