Abstract: This transmission system for transmitting data by a link comprising intermediate equipments (I.sub.1 to I.sub.N) is provided for connecting a transmitting side of a first user equipment (TE) with a receiving side of a second user equipment (TR). In the intermediate equipment situated on the receiving side, thus the most downstream equipment, there is provided a disturbance circuit (30) which disturbs bits at its output as a function of an error information signal that represents the quality of the received information signals in the intermediate equipments.

Abstract: In response to a low-frequency superframe signal, the input frames TRA, TRB of each of two digital channels, shifted in time, are applied each to a frame locking circuit which produces sync signals SYA, SYB; and are also applied to a common cyclic addressing double memory. In the write mode each memory location is addressed to contain a block of TRA and a block of TRB of the same rank controlled by write counters which are incremented by the signals SYA and SYB. Each location has a read counter which is shifted to the more delayed signal of the sync signals SYA and SYB by a phase comparator and a coincidence detector. The output signals having information frames TRA' and TRB' are in phase.

Abstract: Input frames TAR, TARB of each of two diversity digital channels, shifted randomly in time, are applied to respective variable delay memories, which in turn provide in-phase frames on the selection terminals of an output switch. An error masking circuit, including an error detector having various levels of error gravity, and a priority encoder for comparing errors between the two channels and an R-S flip-flop, is connected between each input terminal and a switch control terminal. The better quality frame of the two digital channels is selected and provided as the output signal of the dynamic switching circuitry.