Abstract: A dynamic optimization process of a quality of service (QoS) in a data transmission packet network. The data transmission packet network includes a plurality of sources and a plurality of destinations connected to a transit network by a plurality of access networks. Each source is configured to send data at a maximum data rate and each destination is configured to receive a maximum transmission data rate. The sources each includes a classification and a control device configured to control a transmission data rate of transmitted data. The process is characterized in that the absolute transfer delay period, the jitter, the output of the exchanged data and the losses between each source S and each destination D are measured, and the classification and control means of the output are monitored.

Abstract: The present invention relates to a dynamic optimisation process of quality service in a data transmission packet network (2), where said network (2) consists of a multitude of sources Si and a multitude of destinations Di connected to a transit network (4) via a multitude of access networks (6), where each source is capable of sending a maximum output Lmax,x,x and each destination is capable of receiving a maximum output Lmax,x,d, where said sources each consist of a classification (8) and a control (10) means for the output of transmitted data, a process characterised in that it includes the following stages:

Abstract: A task status word (TSW) is created for each task indicating, the instant location of the task, its priority and a record of synchronizing signals. Task status words are accessible from an addressable memory section for delivery to a TSW register. From the TSW register, a selected TSW effects control functions to synchronize tasks in different processors or computational units as well as input-output processors. A physical memory manager locates TSWs in response to signals, then checks the location of the task and the nature of the signal to determine signal routing to a processor. If a task is not in a processor, an interrupt manager resolves priority and signal significance indicated by the TSW to determine an interrupt.

Abstract: In a pipeline computer, current instructions executed in sequence are monitored for conditional and unconditional branch commands, as well as the readiness of condition codes, the meeting of branch conditions and split commands. A branch command initiates an interval of delay which affords prefetching target instructions while using pipeline contents to prevent a pipeline break and avoid lost time. Detection of a branch command actuates a register to store a sequence of target instructions. Unless a branch command is conditional, subsequent detection (delayed) of a split command shifts the stored target instructions into operation as the current instructions. For a conditional branch command, a jump or split to the target instructions is performed only if the condition is met. Otherwise the current instruction sequence is restored pending another branch command.