Patents by Inventor Jean-Yves Mignolet
Jean-Yves Mignolet has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240000357Abstract: A device for measuring a muscular strength of a lower limb of a patient includes a seat for receiving the patient in a seated position and is suitable for being placed on a substantially horizontal mounting The device further includes an element mechanically coupled to the seat and supporting the lower limb so as to receive at least a portion of the patient's lower limb. A measurement instrument measures a force exerted by the lower limb at the element for supporting the lower limb and is configured to remain substantially immobile with respect to the support upon the application of a force by the patient's lower limb at the element for supporting the lower limb, by virtue of the patient's weight exerted on the seat.Type: ApplicationFiled: November 3, 2021Publication date: January 4, 2024Applicant: MYOCENEInventors: Pierre RIGAUX, Jean-Yves MIGNOLET
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Publication number: 20220142538Abstract: A muscle fatigue determination method including a step of electrostimulating a muscle at an electric charge at different frequencies. The electric charge is determined recursively in order to generate reliable and accurate forces of the muscle in response to the electrostimulation. The method further includes the steps of determining these forces and a muscle fatigue based on them.Type: ApplicationFiled: December 30, 2021Publication date: May 12, 2022Applicant: MYOCENEInventors: Pierre RIGAUX, Jean-Yves MIGNOLET
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Publication number: 20220142509Abstract: A method for determining a muscle fatigue of a muscle includes the step of electrostimulating the muscle at a given electric charge at different frequencies. The method further includes the steps of determining forces developed by the muscle in response to the electrostimulations and determining a muscle fatigue on basis of the forces The steps are repeated a number of times with increasing electric charge, wherein the electric charge is increased by a charge step between two occurrences of the electrostimuation step.Type: ApplicationFiled: June 9, 2021Publication date: May 12, 2022Applicant: MYOCENEInventors: Pierre RIGAUX, Jean-Yves MIGNOLET
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Publication number: 20220142508Abstract: A method for determining a muscle fatigue of a muscle includes the step of electrostimulating the muscle at different frequencies, wherein the electrostimulation includes, at each frequency, a repetition of pulses during a period of time lower than 5 s. The method further includes the steps of determining forces developed by the muscle in response to the electrostimulations of step (i); and determining a muscle fatigue on basis of the determined forces.Type: ApplicationFiled: June 9, 2021Publication date: May 12, 2022Applicant: MYOCENEInventors: Pierre RIGAUX, Jean-Yves MIGNOLET
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Patent number: 9038072Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.Type: GrantFiled: December 10, 2008Date of Patent: May 19, 2015Assignee: XILINX, INC.Inventors: Vincent Nollet, Paul Coene, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest, Theodore Marescaux, Andrei Bartic
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Patent number: 8805548Abstract: The present invention relates to a headband for use in neurostimulation made at least partly of elastic or stretch material comprising: a hole to be located directly on the rear part of the scalp of a user, said hole being sized to fit the inion or occipital protuberantia; at least two electrodes directly attached to the headband and positioned adjacent to and symmetric about said hole, designed so that to be applied on the right and left branch of the occipital nerve respectively, once the inion is put in correspondence with said hole by the user; a connector for connecting a wearable neurostimulator to the headband, said connector being located opposite to said hole, once the headband is worn by the user and means coupled to the elastic or stretch material for electrically connecting said connector and each of said electrodes.Type: GrantFiled: June 10, 2013Date of Patent: August 12, 2014Assignee: STX-Med SprlInventors: Jean-Yves Mignolet, Pierre-Yves Muller, Pierre Rigaux
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Publication number: 20130282095Abstract: The present invention relates to a headband for use in neurostimulation made at least partly of elastic or stretch material comprising: a hole (2) to be located directly on the rear part of the scalp (8) of a user, said hole being sized to fit the inion or occipital protuberantia; at least two electrodes (1) directly attached to the headband and positioned adjacent to and symmetric about said hole (2, designed so that to be applied on the right and left branch of the occipital nerve (7) respectively, once the inion is put in correspondence with said hole (2) by the user; a connector (6A) for connecting a wearable neurostimulator (6) to the headband, said connector (6A) being located opposite to said hole (2), once the headband is worn by the user and means coupled to the elastic or stretch material for electrically connecting said connector (6A) and each of said electrodes (1).Type: ApplicationFiled: June 10, 2013Publication date: October 24, 2013Applicant: STX-Med SprlInventors: Jean-Yves Mignolet, Pierre-Yves Muller, Pierre Rigaux
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Patent number: 8020163Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).Type: GrantFiled: November 24, 2004Date of Patent: September 13, 2011Assignees: Interuniversitair Microelektronica Centrum (IMEC), Xilinx, Inc.Inventors: Vincent Nollet, Paul Coene, Theodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest
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Publication number: 20090187756Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.Type: ApplicationFiled: December 10, 2008Publication date: July 23, 2009Applicant: INTERUNIVERSITAIR MICROELEKTRONICA CENTRUM (IMEC)Inventors: Vincent Nollet, Paul Coene, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest, Theodore Marescaux, Andrei Bartic
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Publication number: 20050203988Abstract: Network on Chip (NoC) Devices, especially Heterogeneous Multiprocessor Network on Chip Devices are described, that optionally contain Reconfigurable Hardware Tiles, as well as Methods and Operating Systems (OS) for Control thereof. In accordance with an aspect of the present invention the Operating Systems handle either (a) run-time traffic management methods or (b) task migration methods, or a combination of these methods. The Operating Systems may be partly distributed but with a centralized master. The traffic management methods and apparatus of the invention use a statistical QoS approach. A system is described having an at least dual Network on Chip as well as methods of operating the same. The system has at least an on-chip communications network, comprising a first on-chip data traffic network (data NoC) and a second on-chip control traffic network (control NoC), having a control network interface component (control NIC) and a data network interface component (data NIC).Type: ApplicationFiled: November 24, 2004Publication date: September 15, 2005Inventors: Vincent Nollet, Paul Coene, Theodore Marescaux, Prabhat Avasare, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest
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Publication number: 20040049672Abstract: A platform supporting reconfigurable computing, enabling the introduction of reconfigurable hardware into portable devices is described. Dynamic hardware/software multitasking methods for a reconfigurable computing platform including reconfigurable hardware devices such as gate arrays, especially FPGA's, and software, such as dedicated hardware/software operating systems and middleware, adapted for supporting the methods, especially multitasking, are described. A computing platform, which is a heterogeneous multi-processor platform, containing one or more instruction set processors (ISP) and a reconfigurable matrix (for instance a gate array, especially an FPGA), adapted for (dynamic) hardware/software multitasking is described.Type: ApplicationFiled: June 2, 2003Publication date: March 11, 2004Inventors: Vincent Nollet, Paul Coene, Jean-Yves Mignolet, Serge Vernalde, Diederik Verkest, Theodore Marescaux, Andrei Bartic
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Patent number: D1063654Type: GrantFiled: October 18, 2021Date of Patent: February 25, 2025Assignee: MYOCENEInventors: Pierre Rigaux, Jean-Yves Mignolet