Patents by Inventor Jeanna N. Matthews

Jeanna N. Matthews has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 8347141
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Grant
    Filed: April 14, 2011
    Date of Patent: January 1, 2013
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
  • Publication number: 20110283139
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Application
    Filed: April 14, 2011
    Publication date: November 17, 2011
    Inventors: Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
  • Patent number: 7970989
    Abstract: A hard disk cache includes entries to be written to a disk, and also includes ordering information describing the order that they should be written to the disk. Data may be written from the cache to the disk in the order specified by the ordering information. In some situations, data may be written out of order. Further, in some situations, clean data from the cache may be combined with dirty data from the cache when performing a cache flush.
    Type: Grant
    Filed: June 30, 2006
    Date of Patent: June 28, 2011
    Assignee: Intel Corporation
    Inventor: Jeanna N. Matthews
  • Patent number: 7962785
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Grant
    Filed: November 18, 2008
    Date of Patent: June 14, 2011
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
  • Patent number: 7886110
    Abstract: A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size of the respectively queues for the cache and mass memory. For write requests, the choice may be based on how many erase blocks are available in the cache.
    Type: Grant
    Filed: December 27, 2007
    Date of Patent: February 8, 2011
    Assignee: Intel Corporation
    Inventor: Jeanna N. Matthews
  • Patent number: 7797479
    Abstract: A technique includes performing a plurality of write operations to store data in different physical memory locations. Each of the physical memory locations are associated with a logical address that is shared in common among the physical addresses. The technique includes storing sequence information in the physical memory locations to indicate which one of the write operations occurred last.
    Type: Grant
    Filed: June 30, 2005
    Date of Patent: September 14, 2010
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Robert W. Faber, Rick Coulson, Jeanna N. Matthews
  • Patent number: 7640395
    Abstract: In one embodiment, the present invention includes a method for maintaining a sequence of writes into a disk cache, where the writes correspond to disk write requests stored in the disk cache, and ordering cache writes from the disk cache to a disk drive according to the sequence of writes. In this way, write ordering from an operating system to a disk subsystem is maintained. Other embodiments are described and claimed.
    Type: Grant
    Filed: March 30, 2006
    Date of Patent: December 29, 2009
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, Sanjeev N. Trika, Jeanna N. Matthews, Robert W. Faber
  • Patent number: 7627713
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Grant
    Filed: December 29, 2005
    Date of Patent: December 1, 2009
    Assignee: Intel Corporation
    Inventors: Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
  • Patent number: 7558911
    Abstract: Processor-based systems may use more than one operating system and may have disk drives which are cached. Systems which include a write-back cache and a disk drive may develop incoherent data when operating systems are changed or when disk drives are removed. Scrambling a partition table on a disk drive and storing cache identification information may improve data coherency in a processor-based system.
    Type: Grant
    Filed: December 18, 2003
    Date of Patent: July 7, 2009
    Assignee: Intel Corporation
    Inventors: John I. Garney, Robert J. Royer, Jr., Jeanna N. Matthews, Kirk D. Brannock
  • Publication number: 20090172249
    Abstract: A dynamic cache policy manager for a mass memory may be used to decide whether a data request is to be routed to the cache or directly to the mass memory, based on estimated delays in processing the request. The choice may be based, at least partially, on the size of the respectively queues for the cache and mass memory. For write requests, the choice may be based on how many erase blocks are available in the cache.
    Type: Application
    Filed: December 27, 2007
    Publication date: July 2, 2009
    Inventor: Jeanna N. Matthews
  • Publication number: 20090077313
    Abstract: A volatile or nonvolatile cache memory can cache mass storage device read data and write data. The cache memory may become inaccessible, and I/O operations may go directly to the mass storage device, bypassing the cache memory. A log of write operations may be maintained to update the cache memory when it becomes available.
    Type: Application
    Filed: November 18, 2008
    Publication date: March 19, 2009
    Inventors: Sanjeev N. Trika, Michael K. Eschmann, Jeanna N. Matthews, Vasudevan Srinivasan
  • Patent number: 7401188
    Abstract: A method, device, and system are disclosed. In one embodiment, the method comprises setting a threshold length for data allowed in a cache, inserting data into the cache during a read or a write request if the length of the data requested is less than the threshold length, and not inserting data into the cache during a read or write request if the length of the data requested is greater than or equal to the threshold length.
    Type: Grant
    Filed: June 29, 2005
    Date of Patent: July 15, 2008
    Assignee: Intel Corporation
    Inventor: Jeanna N. Matthews
  • Patent number: 7360015
    Abstract: In one embodiment of the present invention, a method may include determining whether requested information is part of a streaming access, and directly writing the requested information from a storage device to a memory if the requested information is part of the streaming access. Alternately, if the requested information is not part of the streaming access, it may be written from the storage device to a cache. In various embodiments, the cache may be a non-volatile disk cache.
    Type: Grant
    Filed: May 4, 2004
    Date of Patent: April 15, 2008
    Assignee: Intel Corporation
    Inventors: Jeanna N. Matthews, John I. Garney
  • Publication number: 20080005465
    Abstract: A hard disk cache includes entries to be written to a disk, and also includes ordering information describing the order that they should be written to the disk. Data may be written from the cache to the disk in the order specified by the ordering information. In some situations, data may be written out of order. Further, in some situations, clean data from the cache may be combined with dirty data from the cache when performing a cache flush.
    Type: Application
    Filed: June 30, 2006
    Publication date: January 3, 2008
    Inventor: Jeanna N. Matthews
  • Patent number: 7127571
    Abstract: A method and system to adjust a non-volatile cache associativity are described. In one embodiment, the method and system include determining a status of the system; and setting an associativity level of the non-volatile memory cache (NVC) of the system, based on that status of the system. In one embodiment, the non-volatile memory unit is a cache of the hard disk. Furthermore, in one embodiment, determining the status of the system includes determining whether the system is a mobile computer, and if so, determining whether the system is receiving power from a battery source or AC power from a wall outlet.
    Type: Grant
    Filed: December 30, 2003
    Date of Patent: October 24, 2006
    Assignee: Intel Corporation
    Inventors: Andrew S. Grover, Jeanna N. Matthews
  • Patent number: 6920533
    Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.
    Type: Grant
    Filed: June 27, 2001
    Date of Patent: July 19, 2005
    Assignee: Intel Corporation
    Inventors: Richard L. Coulson, John I. Garney, Jeanna N. Matthews, Robert J. Royer
  • Patent number: 6839812
    Abstract: Briefly, in accordance with an embodiment of the invention, a method and system to store cache metadata from a higher latency media in a lower latency media is provided.
    Type: Grant
    Filed: December 21, 2001
    Date of Patent: January 4, 2005
    Assignee: Intel Corporation
    Inventors: Robert J. Royer, Jr., Jeanna N. Matthews
  • Publication number: 20030120868
    Abstract: Briefly, in accordance with an embodiment of the invention, a method and system to store cache metadata from a higher latency media in a lower latency media is provided.
    Type: Application
    Filed: December 21, 2001
    Publication date: June 26, 2003
    Inventors: Robert J. Royer, Jeanna N. Matthews
  • Publication number: 20030005223
    Abstract: A system and method to reduce the time for system initializations is disclosed. In accordance with the invention, data accessed during a system initialization is loaded into a non-volatile cache and is pinned to prevent eviction. By pinning data into the cache, the data required for system initialization is pre-loaded into the cache on a system reboot, thereby eliminating the need to access a disk.
    Type: Application
    Filed: June 27, 2001
    Publication date: January 2, 2003
    Inventors: Richard L. Coulson, John I. Garney, Jeanna N. Matthews, Robert J. Royer