Patents by Inventor Jeanne H. RAYMOND

Jeanne H. RAYMOND has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 9865486
    Abstract: Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax.
    Type: Grant
    Filed: March 29, 2016
    Date of Patent: January 9, 2018
    Assignee: GLOBALFOUNDRIES Inc.
    Inventors: Igor Arsovski, Jeanne P. Bickford, Mark W. Kuemerle, Susan K. Lichtensteiger, Jeanne H. Raymond
  • Publication number: 20170287756
    Abstract: Systems and methods for optimizing timing/power risk SVB using a customer-supplied, non-linear voltage slope. Chips are manufactured according to an integrated circuit design. The minimum operating voltage and hardware variations for each device in the design is determined and a process distribution for the chips is divided into process windows. Vmax and Vmin to support system frequency are determined for each process window. Vmin vs. process-bin mean and sigma sensitivity is calculated using information about specific devices. The voltage for each process window that generates Vmin for specific devices is identified. Power at the slow end and fast end of each process window is evaluated using the voltage to support system frequency. Pmax is determined. Vmax for each process window that generates Pmax is determined. A voltage is identified between Vmin and Vmax that maximizes the timing margin for system frequency while minimizing risk for Pmax.
    Type: Application
    Filed: March 29, 2016
    Publication date: October 5, 2017
    Applicant: GLOBALFOUNDRIES INC.
    Inventors: IGOR ARSOVSKI, JEANNE P. BICKFORD, MARK W. KUEMERLE, SUSAN K. LICHTENSTEIGER, JEANNE H. RAYMOND
  • Patent number: 9772374
    Abstract: Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.
    Type: Grant
    Filed: October 4, 2012
    Date of Patent: September 26, 2017
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne P. Bickford, Kevin K. Dezfulian, Susan K. Lichtensteiger, Jeanne H. Raymond
  • Patent number: 9152168
    Abstract: Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.
    Type: Grant
    Filed: September 6, 2012
    Date of Patent: October 6, 2015
    Assignee: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne P. Bickford, Rebecca A. Bickford, Susan K. Lichtensteiger, Jeanne H. Raymond
  • Publication number: 20140100799
    Abstract: Methods and structures for leakage screening are disclosed. A method includes sorting devices manufactured from the same device design into voltage bins corresponding to a respective supply voltage. The method further includes determining a respective total power of each of the voltage bins. The method further includes determining a respective uplift power of the voltage bins. The method further includes determining a respective first leakage screen value for each of the voltage bins based on the respective uplift power of each of the voltage bins.
    Type: Application
    Filed: October 4, 2012
    Publication date: April 10, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne P. BICKFORD, Kevin K. DEZFULIAN, Susan K. LICHTENSTEIGER, Jeanne H. RAYMOND
  • Publication number: 20140068283
    Abstract: Methods and systems for system power estimation are provided. A method implemented in a computer infrastructure includes separating products into different segments. The method also includes calculating a power estimation for each segment based on operating conditions of each respective segment. The method further includes calculating an average system power estimation. At least one of the separating, calculating the power estimation, and calculating the average system power estimation is performed using a processor.
    Type: Application
    Filed: September 6, 2012
    Publication date: March 6, 2014
    Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATION
    Inventors: Jeanne P. BICKFORD, Rebecca A. BICKFORD, Susan K. LICHTENSTEIGER, Jeanne H. RAYMOND