Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.

Abstract: The present disclosure generally provides for a method of managing semiconductor manufacturing defects. The method includes: determining a cumulative aging parameter for each of a plurality of first IC products produced with a particular manufacturing line, the cumulative aging parameter being dependent on a product operating condition; calculating an observed defect rate for the plurality of first IC products based on a difference between a predicted value of the aging parameter and the cumulative aging parameter for each of the plurality of first IC products; and adjusting a manufacturing reliability model for the particular manufacturing line in response to the observed defect rate being different from a predicted defect rate for the plurality of first IC products.

Abstract: The present disclosure generally provides for a method of managing semiconductor manufacturing defects. The method includes: determining a cumulative aging parameter for each of a plurality of first IC products produced with a particular manufacturing line, the cumulative aging parameter being dependent on a product operating condition; calculating an observed defect rate for the plurality of first IC products based on a difference between a predicted value of the aging parameter and the cumulative aging parameter for each of the plurality of first IC products; and adjusting a manufacturing reliability model for the particular manufacturing line in response to the observed defect rate being different from a predicted defect rate for the plurality of first IC products.

Abstract: A method of managing semiconductor manufacturing defects, the method including: determining a cumulative aging parameter for each of a plurality of first IC products produced with a particular manufacturing line, the cumulative aging parameter being dependent on a product operating condition; calculating an observed defect rate for the plurality of first IC products based on a difference between a predicted value of a aging parameter and the cumulative aging parameter for each of the plurality of first IC products; and adjusting a manufacturing reliability model for the particular manufacturing line in response to the observed defect rate being different from an initial predicted defect rate for the plurality of first IC products wherein the manufacturing reliability model reestablishes the initial predicted defect rate.

Abstract: A computer-implemented method for evaluating a circuit design to protect a plurality of metal connections from current pulse damage, the method includes receiving a circuit design including the plurality of metal connections and evaluating a maximum peak current of one or more of the plurality of metal connections. The method further includes determining a peak current threshold for the plurality of metal connections based on physical characteristics of the plurality of metal connection and responsive to determining that the maximum peak current of the one or more of the plurality of metal connections exceeds the peak current threshold, performing a peak current design modification to modify the plurality of metal connections in the circuit design.

Abstract: Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.

Abstract: The present disclosure generally provides for a method of managing semiconductor manufacturing defects. The method includes: determining a cumulative aging parameter for each of a plurality of first IC products produced with a particular manufacturing line, the cumulative aging parameter being dependent on a product operating condition; calculating an observed defect rate for the plurality of first IC products based on a difference between a predicted value of the aging parameter and the cumulative aging parameter for each of the plurality of first IC products; and adjusting a manufacturing reliability model for the particular manufacturing line in response to the observed defect rate being different from a predicted defect rate for the plurality of first IC products.

Abstract: A remaining time to replace can be updated taking into account time variation of a failure mechanism of a device. Starting with an initial remaining time to replace, an effective operating time can be determined periodically based on an operating parameter measured at a tracking interval, and remaining time to replace can be updated by subtracting the effective operating time. The technique can be applied to multiple failure mechanisms and to multiple devices and/or components each having multiple failure mechanisms.

Abstract: Various embodiments include approaches for controlling a supply voltage or a clock frequency to an integrated circuit (IC). Various additional embodiments include circuitry for controlling a supply voltage or a clock frequency of an IC. In some cases, a method includes: locating a set of temperature sensors on bin locations in an IC; determining temperature bounds of the bin locations in the IC as a function of a determined temperature at the set of temperature sensors; determining timing constraints as a function of supply voltages at the bin locations and the determined temperature at the set of temperature sensors; and determining operational voltage bounds for the IC as a function of the determined temperature at the set of temperature sensors.

Abstract: Embodiments of the present invention disclose an apparatus and method to determine the intra-chip variation of an integrated circuit. In an embodiment, an apparatus comprises a test macro that includes two or more test structures; wherein each test structure includes identical copies of the same performance monitor; wherein each performance monitor has a unique bounding circuitry that encompasses the performance monitor; and wherein the two or more test structures are positioned close enough to each other as to reduce systematic across chip variation between the two or more test structures.

Abstract: A remaining time to replace can be updated taking into account time variation of a failure mechanism of a device. Starting with an initial remaining time to replace, an effective operating time can be determined periodically based on an operating parameter measured at a tracking interval, and remaining time to replace can be updated by subtracting the effective operating time. The technique can be applied to multiple failure mechanisms and to multiple devices and/or components each having multiple failure mechanisms.

Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design—variable EM limit of each pre-defined circuit.

Abstract: In one embodiment, at least one design library element having a design marker shape is applied to a yield checking tool having library element types, each having a yield checking deck threshold and a marker shape. The design marker shape is compared to each of the marker shapes. A determination is made as to whether the design library element satisfies the yield checking deck threshold associated with the library element type having a matching marker shape. In another embodiment, a product design formed from a design library elements each having a design marker shape is applied to the yield checking tool in a similar manner. In instances where the design library elements do not satisfy the yield checking deck threshold, then the design library element is updated by modifying the design library elements, placement of the design library elements in the product design, and/or wiring connecting the design library elements.

Abstract: Various embodiments include computer-implemented methods, computer program products and systems for terminal metal connector inspection. In some embodiments, a computer-implemented method for identifying a set of critical terminal metal connectors (TMCs) in an integrated circuit (IC) layout includes: identifying a group of necessary terminal metal connectors (TMCs) in the IC layout to form a first portion of the set of critical TMCs; forming a rule including a limit on a number of redundant connections that can be noncompliant between each terminal metal connector (TMC) and a connecting surface in the IC layout without impacting a circuit parameter; and inspecting at least one of the IC layout or the connecting surface to identify each TMC that violates the rule, wherein each identified TMC that violates the rule forms a second portion of the set of critical TMCs.

Abstract: Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.

Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.

Abstract: Solutions for efficiently implementing a via into a multi-level integrated circuit layout are disclosed. In various embodiments, a method of creating a multi-level integrated circuit layout with at least one via is disclosed, the method including: providing at least two layers of the multi-level integrated circuit layout; and selecting a via for connecting the at least two layers, wherein the selecting includes retrieving the via from a via library including a plurality of via types, the plurality of via types prioritized in the via library according to a predicted manufacturing yield for each of the plurality of vias.

Abstract: A method of designing an integrated circuit includes modifying a design attribute-variable electromigration (EM) limit for each pre-defined circuit based on at least one reliability constraint in order to avoid EM violations of an integrated circuit. The method further includes synthesizing the integrated circuit from a high level description to at least a subset of the pre-defined circuit devices using the modified design-variable EM limit of each pre-defined circuit.

Abstract: A system that registers the relationship of use and dependencies in a master source database (i.e., a registration schema) thereby providing cohesiveness between the master source data and downstream systems that receive the master source data fields. The registration schema provides rules for a generic data bridge which executes the movement of master source database data to downstream systems, providing further cohesive connection between what was registered for use and dependencies and what actually occurs in the movement of data to downstream systems. The generic data bridge's actions, on a field-by-field basis, are documented in a use and dependency model. In addition, modification of the use and dependencies registration section of the master source database allows changes to made as opposed to having to modify specific system bridges.

Abstract: A method and structure for forecasting financial obligations for processing mask orders for semiconductor chips includes preparing a relational database of part numbers of graphical data and common mask order descriptions, processing a mask order through the relational database to output part numbers, predicting costs of manufacturing a mask associated with the mask order, and altering aspects of the mask order to produce a change on the costs of manufacturing the mask.