Abstract: A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.

Abstract: A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.

Abstract: A system and method is provided for optimizing semiconductor power by integration of physical design timing and product performance measurements. The method includes: establishing a timing run and identifying a sigma code for the timing run; establishing ring oscillator bins and respective code; identifying a required timing run for a second level assembly to satisfy a selected voltage bin; timing a product using the required timing run; testing a ring oscillator of the product using the timing to obtain physical design identification; recording the physical design identification and the sigma code for the timing run; and using the recorded physical design identification and the sigma code to set a voltage for the product to optimize power.

Abstract: A method for predicting and controlling leakage wherein an IDDQ prediction macro is placed in a plurality of design topographies and data is collected using the IDDQ prediction macro. The IDDQ prediction macro is configured to measure subthreshold leakage and gate leakage for at least one device type in a semiconductor test site and in scribe lines using the IDDQ prediction macro and establish a leakage model. The method correlates the semiconductor test site measurements and the scribe line measurements to establish scribe line control limits, predicts product leakage; and sets subthreshold leakage limits and gate leakage limits for each product using the leakage model.