Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.

Abstract: An apparatus, method, and program product are provided to predict yield loss associated with performance screens or leakage screens. A leakage model is correlated to an on-chip measurement. Current limited yields are determined from the leakage model. A database is formed relating performance sigma cut-points to the circuit limited yields. A product is quoted based on the circuit limited yield for one of the performance sigma cut-points taken from the database. The quote is tied to the product design and testing.

Abstract: A method is provided for predicting leakage current in a semiconductor die with a plurality of devices. A limited leakage macro is incorporated on the semiconductor die. The limited leakage macro is initially tested to measure a leakage current before testing devices outside the limited leakage macro. The measured leakage current is compared to a threshold value for the leakage current. If the leakage current exceeds the threshold value, probe testing is terminated. If, however, the leakage current does not exceed the threshold value, testing continues for devices outside of the limited leakage macro.

Abstract: A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric acceptance criteria. An on-chip parametric measurement macro is included in a design of each semiconductor chip for each identified on-chip parametric measurement structure. Each on-chip parametric measurement macro is tested to determine compliance of the semiconductor chip to the set of parametric acceptance criteria. Compliance to the set of parametric acceptance criteria is validated.

Abstract: A method, apparatus, system, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: A method, apparatus, and computer program product that performs yield estimates using critical area analysis on integrated circuits having redundant and non-redundant elements. The non-redundant elements are ignored or removed from the critical area analysis performed for undesired opens.

Abstract: A method of accepting semiconductor chips is provided using on-chip parametric measurements. An on-chip parametric measurement structure is determined for each parameter in a set of parametric acceptance criteria. An on-chip parametric measurement macro is included in a design of each semiconductor chip for each identified on-chip parametric measurement structure. Each on-chip parametric measurement macro is tested to determine compliance of the semiconductor chip to the set of parametric acceptance criteria. Compliance to the set of parametric acceptance criteria is validated.

Abstract: A parametric-based design methodology interlocks the design of library elements used in a semiconductor product design with the testing protocol used for the resulting semiconductor products such that parametric assumptions made regarding library elements used in a semiconductor product design may be used to disposition products such as semiconductor chips incorporating a semiconductor product design. In particular, a parametric measurement element is incorporated into a product design along with one or more library elements, with the parametric measurement element used to test one or more parametric design points that are associated with the library elements when the product design is used in a manufactured product.

Abstract: A parametric-based design methodology interlocks the design of library elements used in a semiconductor product design with the testing protocol used for the resulting semiconductor products such that parametric assumptions made regarding library elements used in a semiconductor product design may be used to disposition products such as semiconductor chips incorporating a semiconductor product design. In particular, a parametric measurement element is incorporated into a product design along with one or more library elements, with the parametric measurement element used to test one or more parametric design points that are associated with the library elements when the product design is used in a manufactured product.