Abstract: A PLL circuit is provided that comprises a frequency divider that generates a divided frequency signal and a phase frequency detector that receives the divided frequency signal and a reference frequency signal and that is arranged for outputting a first signal for increasing the frequency of an output signal and a second signal for decreasing the frequency of the output signal. Further, there is provided a signal modification unit that receives the first and second signals and that comprises a pulse selector selecting a signal pulse in one of the first and second signals, and a pulse generator for generating a signal pulse simultaneously with the selected signal pulse and adding the generated signal pulse to the other one of the first and second signals.