Patents by Inventor Jeannette M. Jacques

Jeannette M. Jacques has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Methods to facilitate etch uniformity and selectivity
    Patent number: 7341941
    Abstract: A semiconductor device is fabricated with energy based process(es) that alter etch rates for dielectric layers within damascene processes. A first interconnect layer is formed over a semiconductor body. A first dielectric layer is formed over the first interconnect layer. An etch rate of the first dielectric layer is altered. A second dielectric layer is formed on the first dielectric layer. An etch rate of the second dielectric layer is then altered. A trench etch is performed to form a trench cavity within the second dielectric layer. A via etch is performed to form a via cavity within the first dielectric layer. The cavities are filled with conductive material and then planarized to remove excess fill material.
    Type: Grant
    Filed: August 19, 2005
    Date of Patent: March 11, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Ting Y. Tsui, Jeannette M. Jacques, Robert Kraft, Ping Jiang
  • Method to increase mechanical fracture robustness of porous low k dielectric materials
    Patent number: 7342315
    Abstract: The present invention provides an insulating layer 100 for an integrated circuit 110 comprising a porous silicon-based dielectric layer 120 located over a substrate 130. The insulating layer comprises a densified layer 140 comprising an uppermost portion 142 of the porous silicon-based dielectric layer.
    Type: Grant
    Filed: April 25, 2005
    Date of Patent: March 11, 2008
    Assignee: Texas Instruments Incorporated
    Inventors: Ting Yiu Tsui, Andrew John McKerrow, Jeannette M. Jacques