Abstract: An apparatus and method enables elements of a phase locked loop (PLL) (300). The PLL 300 includes a plurality of elements (202, 203, 204, 205). Each element produces an output signal (207, 208, 209, 116 or 117). Each element has a response time (t3−t2) defined by the difference in time between a first time (t2) at which the element is enabled and a second time (t3), occurring after the first time (t2), at which the output signal of the element reaches a steady state condition. A voltage controlled oscillator (204) of the plurality of elements, having a first response time (t3−t2) is enabled at the first time (t2) responsive to a first control signal (302). A loop divider (205) of the plurality of elements, having a second response time less than the first response time (t3−t2), is enabled responsive to the first response time (t3−t2) and a second control signal (303). The present invention advantageously provides fast lock time for the PLL (300).

Abstract: A data processing apparatus (200) which improves the accuracy of resultant data. The data processing apparatus includes an input (220, 222) configured to receive input data. The input data includes data corresponding to an input coefficient to be multiplied by the square root of two (.sqroot.2) and input addend. The data processing apparatus further includes a first memory (202) for storing a coefficient of the square root of two, a second memory (204) for storing an addend, a summer (206, 208) which independently sums the input coefficient and the coefficient to produce a combined coefficient and sums the input addend and the addend to produce an addend sum, a multiplier (210) which multiplies the combined coefficient and an approximation of the square root of two to produce an intermediate result, and a summer (214) which sums the intermediate result and the addend sum to produce the resultant data.

Abstract: A voltage reference generator (200) generates a temperature compensated voltage at an output (202). The voltage reference generator includes a first transistor (204) and a second transistor (206) series connected between a supply voltage and the output. The first transistor and the second transistor establishing the temperature compensated voltage in response to a bias current (I.sub.BIAS) and a first bias voltage and a second bias voltage. The voltage reference generator further includes a current source (208) coupled to the first transistor and the second transistor to establish the bias current in the first transistor and the second transistor. The current source produces the first bias voltage and the second bias voltage.

Abstract: A comparator circuit (100) produces a binary output voltage at an output (109) in response to a time varying input signal received at an input (108). The comparator circuit includes an output circuit (106) having a first current mirror (202), a second current mirror (204), a bias circuit (206) and a helping current source (208). Bias currents are applied in response to the state of the output voltage at the output to increase the gain and the hysteresis of the output circuit.

Abstract: An error suppressing circuit (301) and method therefor for a phase locked loop (PLL) (300). According to one embodiment of the present invention, a transient condition, for example, a bandwidth switch, in the PLL (300) is detected. The PLL (300) is opened for a period of time (509) responsive to detecting the transient condition. The phase of a reference frequency signal (115) and the phase of a output frequency signal (116 or 117) are synchronized after a lapse of the period of time (509). The PLL (300) is closed responsive to the phase of the reference frequency signal (115) and the phase of the output frequency signal (116 or 117) being synchronized. The present envention advantageously reduces the length of time it takes for the PLL (300) to correct for the phase and frequency error generated by the transient condition, and is capable of operating with various types of PLLs.

Abstract: The present invention provides a circuit (10) and method for providing a delayed output signal which is less sensitive to supply variation compared to conventional circuits, has high noise immunity, can be operated at high frequency, and occupies a minimum area on the semiconductor. The delay is provided according to the present invention by separately controlling the discharge currents of a capacitor (26) before and after the trip point voltage of an output inverter (16) of the circuit (10) has been reached. The delay interval is determined primarily by the capacitor value, the voltage difference between the supply and the trip point of the output inverter, and the first discharge current, set by a resistor (24) in series with a transistor (34). The second discharge current is set by a switch (36) having a series of transistors (38, 40).

Abstract: In a phase locked loop (PLL) (308), an edge proximity detector (302) identifies a phase error, indicative of a difference between a phase of a reference frequency signal (115) and a phase of an output frequency signal (116 or 117), as either desirable or undesirable. When the phase error is identified as desirable, a counter (301) determines a rate of change of the phase error over a first predetermined time period (412) to provide an indication of frequency error (306) between the frequency of the reference frequency signal (206) and the frequency of the output frequency signal (116 or 117); and a loop bandwidth adjuster (310) controls a transition between a first and a second loop bandwidth state of the PLL (308) responsive to the indication of the frequency error (306). When the phase error is identified as undesirable, the PLL (308) operates in the second loop bandwidth state. The present invention advantageously provides an accurate determination of when to vary the loop bandwidth of the PLL (308).