Patents by Inventor Jed Griffin

Jed Griffin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20160105274
    Abstract: Wireless network throughput system and method implementing ultra phase modulation (UPM). An example system includes a receiver, a transmitter, UPM modulator, UPM demodulator and an ultra-phase coordinator (UPC) circuit connected to the receiver and to the transmitter antennae. The UPM wireless network throughput system and method reduces RF reception to only amplifying, filtering, and demodulating without any down-conversion. In an example, the system includes a frequency memory, wherein a frequency of a signal received at the receiver is recorded and a same frequency is used to transmit a signal in return.
    Type: Application
    Filed: October 14, 2014
    Publication date: April 14, 2016
    Inventor: Jed Griffin
  • Patent number: 9191016
    Abstract: Fast phase coordinating systems and methods are disclosed. An example system includes a phase locator configured to detect a first phase of a reference signal and a first phase of a coordinating signal after the first phase of the reference signal. An integrator is configured to integrate from the first phase of the reference signal to a location phase of the coordinating signal and integrate oppositely from the first phase of the coordinating signal to a time-shifted phase of the reference signal and output the result. A control function is configured to shift the phase of the coordinating signal in response to output from the integrator.
    Type: Grant
    Filed: February 4, 2013
    Date of Patent: November 17, 2015
    Inventor: Jed Griffin
  • Patent number: 8884798
    Abstract: Systems and techniques for performing binary divarication digital-to-analog conversion are described. A described converter includes voltage range adjusters arranged in series to convert a digital sequence to an analog representation, each of the adjusters being responsive to a respective bit of the digital sequence, and a combiner. The first adjuster produces first high and low output voltages based on first high and low input voltages and a most significant bit value of the digital sequence. The last adjuster produces last high and low output voltages based on last high and low input voltages and a least significant bit value of the digital sequence. The last high and low input voltages are responsive to the first high and low output voltages as modified by any of zero or more intermediate voltage range adjusters. The combiner produces an analog output signal based on the last high and low output voltages.
    Type: Grant
    Filed: November 30, 2012
    Date of Patent: November 11, 2014
    Assignee: Atmel Corporation
    Inventor: Jed Griffin
  • Publication number: 20140218085
    Abstract: Fast phase coordinating systems and methods are disclosed. An example system includes a phase locator configured to detect a first phase of a reference signal and a first phase of a coordinating signal after the first phase of the reference signal. An integrator is configured to integrate from the first phase of the reference signal to a location phase of the coordinating signal and integrate oppositely from the first phase of the coordinating signal to a time-shifted phase of the reference signal and output the result. A control function is configured to shift the phase of the coordinating signal in response to output from the integrator.
    Type: Application
    Filed: February 4, 2013
    Publication date: August 7, 2014
    Applicant: GAIN ICS LLC
    Inventor: Jed Griffin
  • Patent number: 8783949
    Abstract: A self-calibrating, wide-range temperature sensor includes a current reference, impervious to process and voltage, with the current reference mirrored into two oppositely-sized bipolar transistors or diodes. Duplicate current sources are used with a ratio of geometries between them, such that the larger current biases the smaller bipolar transistor (less cross-sectional area) and the smaller current source biases the larger bipolar transistor (higher cross-sectional area). The current source in conjunction with the differential temperature sensing provides inherent calibration without drift while the differential sensing, from the ratio of geometries in the current paths also increases sensitivity.
    Type: Grant
    Filed: November 17, 2009
    Date of Patent: July 22, 2014
    Assignee: Atmel Corporation
    Inventors: Jed Griffin, Daniel J. Russell
  • Publication number: 20140062746
    Abstract: Systems and techniques for performing binary divarication digital-to-analog conversion are described. A described converter includes voltage range adjusters arranged in series to convert a digital sequence to an analog representation, each of the adjusters being responsive to a respective bit of the digital sequence, and a combiner. The first adjuster produces first high and low output voltages based on first high and low input voltages and a most significant bit value of the digital sequence. The last adjuster produces last high and low output voltages based on last high and low input voltages and a least significant bit value of the digital sequence. The last high and low input voltages are responsive to the first high and low output voltages as modified by any of zero or more intermediate voltage range adjusters. The combiner produces an analog output signal based on the last high and low output voltages.
    Type: Application
    Filed: November 30, 2012
    Publication date: March 6, 2014
    Applicant: ATMEL CORPORATION
    Inventor: Jed Griffin
  • Patent number: 7994869
    Abstract: The disclosed current-controlled hysteretic oscillator operates by controlled currents opposing each other in differential pairs to set a controlled hysteresis for improved relaxation oscillations with immunity to phase or frequency error.
    Type: Grant
    Filed: April 27, 2009
    Date of Patent: August 9, 2011
    Assignee: Atmel Corporation
    Inventors: Jed Griffin, Miguel Gamarra
  • Patent number: 7990224
    Abstract: A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain.
    Type: Grant
    Filed: April 27, 2007
    Date of Patent: August 2, 2011
    Assignee: Atmel Corporation
    Inventor: Jed Griffin
  • Publication number: 20110116527
    Abstract: A self-calibrating, wide-range temperature sensor includes a current reference, impervious to process and voltage, with the current reference mirrored into two oppositely-sized bipolar transistors or diodes. Duplicate current sources are used with a ratio of geometries between them, such that the larger current biases the smaller bipolar transistor (less cross-sectional area) and the smaller current source biases the larger bipolar transistor (higher cross-sectional area). The current source in conjunction with the differential temperature sensing provides inherent calibration without drift while the differential sensing, from the ratio of geometries in the current paths also increases sensitivity.
    Type: Application
    Filed: November 17, 2009
    Publication date: May 19, 2011
    Applicant: ATMEL CORPORATION
    Inventors: Jed Griffin, Daniel J. Russell
  • Publication number: 20100271143
    Abstract: The disclosed current-controlled hysteretic oscillator operates by controlled currents opposing each other in differential pairs to set a controlled hysteresis for improved relaxation oscillations with immunity to phase or frequency error.
    Type: Application
    Filed: April 27, 2009
    Publication date: October 28, 2010
    Applicant: ATMEL Corporation
    Inventors: Jed Griffin, Miguel Gamarra
  • Patent number: 7629847
    Abstract: An opposing currents (OC) differential amplifier is disclosed that eliminates headroom constraints and other problems associated with conventional differential pair amplifiers with current source biasing. The OC differential amplifier has a higher differential gain and differential gain bandwidth than conventional differential pair amplifiers.
    Type: Grant
    Filed: March 24, 2008
    Date of Patent: December 8, 2009
    Assignee: ATMEL Corporation
    Inventor: Jed Griffin
  • Publication number: 20080266001
    Abstract: A phase-locked loop circuit having a dual-reference input and a phase detector. The dual-reference input is configured to accept both a rising edge of an input clock having a first phase and a falling edge of the input clock having a second phase. The phase detector is coupled to the dual-reference input and is configured to produce a center phase signal based upon and centered in phase between the first and second phases. The phase detector is further configured with a feedback loop to adjust any tracking error and provide a tracking output signal. The phase detector system maintains both a high tracking bandwidth and a bounded jitter amplification based as a result of the dual reference signal. The high tracking bandwidth and the bounded jitter amplification are independent of an applied loop gain.
    Type: Application
    Filed: April 27, 2007
    Publication date: October 30, 2008
    Applicant: ATMEL CORPORATION
    Inventor: Jed Griffin
  • Publication number: 20080101505
    Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal.
    Type: Application
    Filed: October 26, 2007
    Publication date: May 1, 2008
    Inventors: Jed Griffin, Jerry Jex, Arnaud Forestier, Kersi Vakil, Abhimanyu Kolla
  • Publication number: 20070076831
    Abstract: Embodiments of the present invention are directed to a dual-reference delay-locked loop that includes a first delay element that delays a clock signal. The rising phase and the falling phase of the delayed clock signal are used as a first and a second reference phases, respectively, for a phase detector. A second delay element delays the first reference signal with a tracking phase that centers between the two reference phases. The phase detector detects a difference between the average of the reference phases and the tracking or resultant phase and outputs a difference signal that biases the delay elements to slew to the left or the right so that the resultant phase is centered between the reference phases corresponding to the rising and falling edges of the incoming clock.
    Type: Application
    Filed: September 30, 2005
    Publication date: April 5, 2007
    Inventor: Jed Griffin
  • Publication number: 20060242447
    Abstract: Thermal control for a controller in a data processing environment is described. In one embodiment, the invention includes detecting a temperature of a semiconductor device at a thermal sensor on the semiconductor device, comparing the detected temperature to a threshold, and generating a high interrupt if the temperature is above the threshold and a low interrupt if the temperature is below the threshold.
    Type: Application
    Filed: March 23, 2005
    Publication date: October 26, 2006
    Inventors: Sivakumar Radhakrishnan, Michael Wiznerowicz, Jed Griffin, Kapilan Maheswaran, Scott Rushford, David Hotz
  • Publication number: 20060203883
    Abstract: Temperature sensing circuits are provided herein. In some embodiments, they comprise first and second transistors coupled together in a current mirror configuration and first and second diodes. The first diode is coupled to the first transistor, and the second diode is coupled to the second transistor. A temperature sensing signal is generated between the first and second diodes when the circuit is being operated. Other embodiments are disclosed and/or claimed herein.
    Type: Application
    Filed: March 8, 2005
    Publication date: September 14, 2006
    Inventor: Jed Griffin
  • Publication number: 20050018779
    Abstract: In some embodiments, the inventions include a receiver to receive a full cycle encoded signal in which data is represented in data time segments and no data time segment has more than one cycle. The receiver provides a data output signal responsive to the full cycle encoding signal. Other embodiments are described and claimed.
    Type: Application
    Filed: July 23, 2003
    Publication date: January 27, 2005
    Inventors: Jed Griffin, Jerry Jex, Arnaud Forestier, Kersi Vakil, Abhimanyu Kolla
  • Publication number: 20050018761
    Abstract: In some embodiments, the inventions includes a transmitter including a cycle encoding circuit to receive a data input signal and to provide a full cycle encoded signal in response thereto by continuously joining portions of different encoding signals. Some of the encoding signals have a different frequency than others of the encoding signals and some of the encoding signals have a different phase than others of the encoding signals. Data is represented in data time segments of the full cycle encoded signal and no data time segment has more than one cycle of an encoding signal. In some embodiments, a receiver receives the cycle encoded signal and recovers data of the data input signal. Still other embodiments are described and claimed.
    Type: Application
    Filed: July 23, 2003
    Publication date: January 27, 2005
    Inventors: Jerry Jex, Jed Griffin, Arnaud Forestier, Kersi Vakil, Abhimanyu Kolla
  • Patent number: 6624659
    Abstract: In one embodiment of the invention, an update circuit having a bus driver to drive a bus dynamically receives an update compensation code. The bus driver receives data at a data clock signal. The update compensation code controls impedance matching at the bus driver according to the data. A code generator generates the update compensation code at a base clock signal. The base clock signal is synchronized with the data clock signal. The base clock signal has an update interval and a quiet interval. A distribution ring interface distributes the update compensation code to the update circuit synchronously with the base clock signal.
    Type: Grant
    Filed: June 30, 2000
    Date of Patent: September 23, 2003
    Assignee: Intel Corporation
    Inventors: Isaac P. Abraham, David R. Johnson, Jed Griffin, David Peart
  • Patent number: 6621313
    Abstract: A synchronizing apparatus is provided in a high frequency system. The synchronizing apparatus includes a loop control circuit, a voltage controlled oscillator coupled to the loop control circuit, a matched current amplifier coupled to the voltage controlled oscillator, and a duty cycle control buffer connect to the matched circuit amplifier.
    Type: Grant
    Filed: October 23, 2002
    Date of Patent: September 16, 2003
    Assignee: Intel Corporation
    Inventors: Nasser A. Kurd, Jed Griffin