Patents by Inventor Jed Hickory Rankin
Jed Hickory Rankin has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 8598660Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.Type: GrantFiled: June 1, 2011Date of Patent: December 3, 2013Assignee: International Business Machines CorporationInventors: Renata Camillo-Castillo, Erik Mattias Dahlstrom, Robert J. Gauthier, Jr., Ephrem G. Gebreselasie, Richard A. Phelps, Jed Hickory Rankin, Yun Shi
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Publication number: 20130260183Abstract: A solid-state battery structure having a plurality of battery cells formed in a substrate. The plurality of battery cells includes a first current collector layer overlying a first insulating layer and a first electrode layer overlying the first current collector layer. The battery structure further includes a second current collector layer overlying a patterned second electrode layer. The patterned second electrode layer overlies the substrate and forms a plurality of sub-arrays of the battery cells. The battery structure further includes a second insulating layer overlying the second current collector layer. The second insulating layer substantially laterally surrounds first and second contact pads. The first pad is electrically connected to the first current collector layer and the second pad is electrically connected to the second current collector layer. The first and second contact pads are in electrical communication, through at least two electrical wires, with a circuit located upon the substrate.Type: ApplicationFiled: March 28, 2012Publication date: October 3, 2013Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: John Ellis-Monaghan, Jeffrey P. Gambino, Kirk D. Peterson, Jed Hickory Rankin
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Patent number: 8404430Abstract: A multi-chip reticle, methods of designing and fabricating multi-chip reticles, a system for designing a multi-chip reticle, and a method of fabricating integrated circuit chips using the multi-chip reticle. The multi-chip reticle includes a transparent substrate having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images.Type: GrantFiled: August 1, 2011Date of Patent: March 26, 2013Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Jed Hickory Rankin
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Publication number: 20120306014Abstract: A lateral diffused metal-oxide-semiconductor field effect transistor (LDMOS transistor) employs a stress layer that enhances carrier mobility (i.e., on-current) while also maintaining a high breakdown voltage for the device. High breakdown voltage is maintained, because an increase in doping concentration of the drift region is minimized. A well region and a drift region are formed in the substrate adjacent to one another. A first shallow trench isolation (STI) region is formed on and adjacent to the well region, and a second STI region is formed on and adjacent to the drift region. A stress layer is deposited over the LDMOS transistor and in the second STI region, which propagates compressive or tensile stress into the drift region, depending on the polarity of the stress layer. A portion of the stress layer can be removed over the gate to change the polarity of stress in the inversion region below the gate.Type: ApplicationFiled: June 1, 2011Publication date: December 6, 2012Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Renata Camillo-Castillo, Erik Mattias Dahlstrom, Robert J. Gauthier, JR., Ephrem G. Gebreselasie, Richard A. Phelps, Jed Hickory Rankin, Yun Shi
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Patent number: 8238032Abstract: A variable focal point lens includes a transparent tank, which comprises a transparent enclosure containing a transparent flexible membrane separating the inner volume of the transparent tank into an upper tank portion and a lower tank portion. The upper tank portion and the lower tank portion contain liquids having different indices of refraction. The transparent flexible membrane is electrostatically displaced to change the thicknesses of the first tank portion and the second tank portion in the path of the light, thereby shifting the focal point of the lens axially and/or laterally. The electrostatic displacement of the membrane may be effected by a fixed charge in the membrane and an array of enclosure-side conductive structures on the transparent enclosure, or an array of membrane-side conductive structures on the transparent membrane and an array of enclosure-side conductive structures.Type: GrantFiled: February 19, 2010Date of Patent: August 7, 2012Assignee: International Business Machines CorporationInventors: John Joseph Ellis-Monaghan, Jeffrey Peter Gambino, Kirk David Peterson, Jed Hickory Rankin
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Patent number: 8084822Abstract: Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.Type: GrantFiled: September 30, 2009Date of Patent: December 27, 2011Assignee: International Business Machines CorporationInventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Jed Hickory Rankin, Robert R. Robison, William Robert Tonti
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Publication number: 20110287349Abstract: A multi-chip reticle, methods of designing and fabricating multi-chip reticles, a system for designing a multi-chip reticle, and a method of fabricating integrated circuit chips using the multi-chip reticle. The multi-chip reticle includes a transparent substrate having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images.Type: ApplicationFiled: August 1, 2011Publication date: November 24, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Alan Anderson, Jed Hickory Rankin
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Patent number: 8021803Abstract: A multi-chip reticle, methods of designing and fabricating multi-chip reticles, a system for designing a multi-chip reticle, and a method of fabricating integrated circuit chips using the multi-chip reticle. The multi-chip reticle includes a transparent substrate having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images.Type: GrantFiled: June 12, 2009Date of Patent: September 20, 2011Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Jed Hickory Rankin
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Publication number: 20110073951Abstract: Fin-FETS and methods of fabricating fin-FETs. The methods include: providing substrate comprising a silicon oxide layer on a top surface of a semiconductor substrate, a stiffening layer on a top surface of the silicon oxide layer, and a single crystal silicon layer on a top surface of the stiffening layer; forming a fin from the single crystal silicon layer; forming a source and a drain in the fin and on opposite sides of a channel region of the fin; forming a gate dielectric layer on at least one surface of the fin in the channel region; and forming a gate electrode on the gate dielectric layer.Type: ApplicationFiled: September 30, 2009Publication date: March 31, 2011Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Kiran V. Chatty, Robert J. Gauthier, JR., Jed Hickory Rankin, Robert R. Robison, William Robert Tonti
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Publication number: 20100316938Abstract: A multi-chip reticle, methods of designing and fabricating multi-chip reticles, a system for designing a multi-chip reticle, and a method of fabricating integrated circuit chips using the multi-chip reticle. The multi-chip reticle includes a transparent substrate having two or more separate chip images arranged in an array, each chip image of said two or more chip images having only one type of reticle image, wherein at least two of said two more chip images have different types of reticle images.Type: ApplicationFiled: June 12, 2009Publication date: December 16, 2010Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Brent Alan Anderson, Jed Hickory Rankin
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Patent number: 7737498Abstract: Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.Type: GrantFiled: May 7, 2008Date of Patent: June 15, 2010Assignee: International Business Machines CorporationInventors: Kiran V. Chatty, Robert J. Gauthier, Jr., Jed Hickory Rankin, Robert R. Robison, William Robert Tonti
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Publication number: 20090278201Abstract: Field effect transistor and methods of fabricating field effect transistors. The field effect transistors includes: a semiconductor substrate; a silicon oxide layer on the substrate; a stiffening layer on the silicon oxide layer; a single crystal silicon layer on the stiffening layer; a source and a drain on opposite sides of a channel region of the silicon layer; a gate electrode over the channel region and a gate dielectric between the gate electrode and the channel region.Type: ApplicationFiled: May 7, 2008Publication date: November 12, 2009Inventors: Kiran V. Chatty, Robert J. Gauthier, JR., Jed Hickory Rankin, Robert R. Robison, William Robert Tonti
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Patent number: 7541613Abstract: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.Type: GrantFiled: May 8, 2008Date of Patent: June 2, 2009Assignee: International Business Machines CorporationInventors: Brent Alan Anderson, Shahid Ahmad Butt, Allen H. Gabor, Patrick Edward Lindo, Edward Joseph Nowak, Jed Hickory Rankin
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Patent number: 7525646Abstract: A system and method of operation for a lithographic system having multiple exposure stations sharing one or more post-expose bake station and a centralized control system that schedules work through the expose station to the post-expose bake station while taking into consideration the patterning time for work pieces to be scheduled as well as the amount of post-expose delay allowable for the exposed work pieces.Type: GrantFiled: March 27, 2008Date of Patent: April 28, 2009Assignee: International Business Machines CorporationInventors: Daniel Boyd Sullivan, Brain Neal Caldwell, Adam Charles Smith, Jed Hickory Rankin
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Patent number: 7507506Abstract: A method of printing multi-layer masks includes analyzing masking requirements of the photomask includes creating pairings of all masking layers requiring substantially similar processing, wherein the pairings include less critical sub-fields that are capable of printing on laser lithography tools, and more critical sub-fields that require e-beam for printing, coating the photomask with a photoresist, exposing the less critical sub-fields and non-critical mask patterns on a laser mask writer where a maximum image size and image placement control are not required, moving the photomask to an e-beam mask writing tool, exposing the more critical sub-fields and patterns that require a maximum image size and placement control with the e-beam mask writing tool, developing the photoresist to reveal latent images that are formed in the e-beam mask writing tool and laser mask writer, transferring pattern of the photoresist to an underlying masking layer using one of direct chemical attack or reactive-ion etching, and rType: GrantFiled: June 30, 2008Date of Patent: March 24, 2009Assignee: International Business Machines CorporationInventors: Brent A. Anderson, Jed Hickory Rankin
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Patent number: 7491476Abstract: The present invention relates to a method, apparatus, and system for monitoring photomasks used in the production of semiconductor wafers for defects, degradation or a combination thereof. The invention provides an integrated test structure on the photomask itself and a method of positioning the test structure in conjunction with the photomask for a masking layer of an integrated circuit. The integrated test structures provide for an in-situ electrical or electromagnetic monitor on the photomask that doesn't adversely affect the integrated semiconductor devices on the wafers during the lithographic masking process.Type: GrantFiled: April 16, 2008Date of Patent: February 17, 2009Assignee: International Business Machines CorporationInventors: Jed Hickory Rankin, Brent Alan Anderson
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Publication number: 20080261122Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and a top surface; the non-printable region comprising a second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and a top surface; and a capping layer on the sidewalls of the first opaque regions and the sidewalls of the second opaque region.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Jeffrey Peter Gambino, Robert Kenneth Leidy, Kirk David Peterson, Jed Hickory Rankin, Edmund Juris Sprogis
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Publication number: 20080261120Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Jeffrey Peter Gambino, Robert Kenneth Leidy, Kirk David Peterson, Jed Hickory Rankin, Edmund Juris Sprogis
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Publication number: 20080261121Abstract: A photomask and a method of fabricating the photomask. The photomask including: a substrate transparent to a selected wavelength or wavelengths of radiation, the substrate having a top surface and an opposite bottom surface, the substrate having a printable region and a non-printable region; the printable region having first opaque regions raised above the top surface of the substrate adjacent to clear regions, each opaque region of the first opaque regions having sidewalls and opposite top and bottom surfaces, the first opaque regions including a metal; the non-printable region including metal second opaque region raised above the top surface of the substrate, the second opaque region having sidewalls and opposite top and bottom surface, the second opaque regions including the metal; and a conformal protective metal oxide capping layer on top surfaces and sidewalls of the first and second opaque regions. The conformal layer is formed by oxidation.Type: ApplicationFiled: April 20, 2007Publication date: October 23, 2008Inventors: Jeffrey Peter Gambino, Robert Kenneth Leidy, Kirk David Peterson, Jed Hickory Rankin, Edmund Juris Sprogis
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Publication number: 20080246097Abstract: A method of reducing parametric variation in an integrated circuit (IC) chip and an IC chip with reduced parametric variation. The method includes: on a first wafer having a first arrangement of chips, each IC chip divided into a second arrangement of regions, measuring a test device parameter of test devices distributed in different regions; and on a second wafer having the first arrangement of IC chips and the second arrangement of regions, adjusting a functional device parameter of identically designed field effect transistors within one or more regions of all IC chips of the second wafer based on a values of the test device parameter measured on test devices in regions of the IC chip of the first wafer by a non-uniform adjustment of physical or metallurgical polysilicon gate widths of the identically designed field effect transistors from region to region within each IC chip.Type: ApplicationFiled: May 8, 2008Publication date: October 9, 2008Inventors: Brent Alan Anderson, Shahid Ahmad Butt, Allen H. Gabor, Patrick Edward Lindo, Edward Joseph Nowak, Jed Hickory Rankin