Patents by Inventor Jed W. Pitera
Jed W. Pitera has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Patent number: 10361116Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.Type: GrantFiled: March 20, 2018Date of Patent: July 23, 2019Assignee: International Business Machines CorporationInventors: Hsueh-Chung Chen, Cheng Chi, Lin Hu, Kafai Lai, Chi-Chun Liu, Jed W. Pitera
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Patent number: 10081740Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.Type: GrantFiled: October 10, 2017Date of Patent: September 25, 2018Assignee: International Business Machines CorporationInventors: Joy Cheng, Michael A. Guillorn, Chi-Chun Liu, Jed W. Pitera, Hsinyu Tsai
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Publication number: 20180211869Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.Type: ApplicationFiled: March 20, 2018Publication date: July 26, 2018Inventors: Hsueh-Chung Chen, Cheng Chi, Lin Hu, Kafai Lai, Chi-Chun Liu, Jed W. Pitera
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Patent number: 9984920Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.Type: GrantFiled: July 11, 2016Date of Patent: May 29, 2018Assignee: International Business Machines CorporationInventors: Hsueh-Chung Chen, Cheng Chi, Lin Hu, Kafai Lai, Chi-Chun Liu, Jed W. Pitera
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Patent number: 9884978Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.Type: GrantFiled: June 29, 2015Date of Patent: February 6, 2018Assignee: International Business Machines CorporationInventors: Joy Cheng, Michael A. Guillorn, Chi-Chun Liu, Jed W. Pitera, Hsinyu Tsai
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Publication number: 20180030312Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.Type: ApplicationFiled: October 10, 2017Publication date: February 1, 2018Inventors: Joy Cheng, Michael A. Guillorn, Chi-Chun Liu, Jed W. Pitera, Hsinyu Tsai
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Patent number: 9879152Abstract: Block copolymers (BCPs) for self-assembly applications comprise a linear fluorinated linking group L? joining a pair of adjacent blocks. A film layer comprising a BCP, which is disposed on an underlayer and in contact with an atmosphere, is capable of forming a perpendicularly oriented domain pattern when the underlayer is preferentially wetted by one domain of an otherwise identical self-assembled BCP in which all fluorines of L? are replaced by hydrogen. The BCP can be a low-chi or high-chi BCP. In a preferred embodiment, the BCP comprises a styrene-based first block, and a second block comprises a carbonate and/or ester repeat unit formed by ring opening polymerization of a cyclic carbonate and/or cyclic ester monomer. The linking group L? has a lower surface energy than each of the polymer blocks.Type: GrantFiled: October 21, 2015Date of Patent: January 30, 2018Assignee: International Business Machines CorporationInventors: Noel Arellano, Joy Cheng, Teddie P. Magbitang, Jed W. Pitera, Daniel P. Sanders, Kristin Schmidt, Hoa D. Truong, Ankit Vora
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Publication number: 20180012795Abstract: A method for local pattern density control of a device layout used by graphoepitaxy directed self-assembly (DSA) processes includes importing a multi-layer semiconductor device design into an assist feature system and determining overlapping regions between two or more layers in the multi-layer semiconductor device design using at least one Boolean operation. A fill for assist features is generated to provide dimensional consistency of device features by employing the overlapping regions to provide placement of the assist features. An updated device layout is stored in a memory device.Type: ApplicationFiled: July 11, 2016Publication date: January 11, 2018Inventors: Hsueh-Chung Chen, Cheng Chi, Lin Hu, Kafai Lai, Chi-Chun Liu, Jed W. Pitera
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Publication number: 20170114246Abstract: Block copolymers (BCPs) for self-assembly applications comprise a linear fluorinated linking group L? joining a pair of adjacent blocks. A film layer comprising a BCP, which is disposed on an underlayer and in contact with an atmosphere, is capable of forming a perpendicularly oriented domain pattern when the underlayer is preferentially wetted by one domain of an otherwise identical self-assembled BCP in which all fluorines of L? are replaced by hydrogen. The BCP can be a low-chi or high-chi BCP. In a preferred embodiment, the BCP comprises a styrene-based first block, and a second block comprises a carbonate and/or ester repeat unit formed by ring opening polymerization of a cyclic carbonate and/or cyclic ester monomer. The linking group L? has a lower surface energy than each of the polymer blocks.Type: ApplicationFiled: October 21, 2015Publication date: April 27, 2017Inventors: Noel Arellano, Joy Cheng, Teddie P. Magbitang, Jed W. Pitera, Daniel P. Sanders, Kristin Schmidt, Hoa D. Truong, Ankit Vora
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Patent number: 9581899Abstract: After formation of a template layer over a neutral polymer layer, a self-assembling block copolymer material is applied and self-assembled. The template layer includes a first linear portion, a second linear portion that is shorter than the first linear portion, and blocking template structures having a greater width than the second linear portion. The self-assembling block copolymer material is phase-separated into alternating lamellae in regions away from the widthwise-extending portion. The blocking template structures perturb, and cause termination of, the lamellae. A cavity parallel to the first and second linear portions and terminating in self-alignment to the blocking template structures is formed upon selective removal of a polymeric block component. The pattern of the cavity can be inverted and transferred into the material layer to form fins having different lengths.Type: GrantFiled: November 27, 2012Date of Patent: February 28, 2017Assignee: International Business Machines CorporationInventors: Michael A. Guillorn, Kafai Lai, Jed W. Pitera, Hsinyu Tsai
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Publication number: 20160379837Abstract: The disclosure provides methods for directed self-assembly (DSA) of a block co-polymer (BCP). In one embodiment, a method includes: forming an oxide spacer along each of a first sidewall and a second sidewall of a cavity in a semiconductor substrate; forming a neutral layer between the oxide spacers and along a bottom of the cavity; and removing the oxide spacers to expose the first and second sidewalls and a portion of the bottom of the cavity adjacent the first and second sidewalls.Type: ApplicationFiled: June 29, 2015Publication date: December 29, 2016Inventors: Joy Cheng, Michael A. Guillorn, Chi-Chun Liu, Jed W. Pitera, Hsinyu Tsai
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Patent number: 9298870Abstract: Methods and computer program products for designing topographic patterns for directing the formation of self-assembled domains at specified locations on substrates. The methods include generating mathematical models that operate on mathematical descriptions of the number and locations of cylindrical self-assembled domains in a mathematical description of a guiding pattern.Type: GrantFiled: May 16, 2012Date of Patent: March 29, 2016Assignee: International Business Machines CorporationInventors: Joy Cheng, Kafai Lai, Chi-Chun Liu, Jed W. Pitera, Charles T. Rettner
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Publication number: 20160085896Abstract: Methods and computer program products for designing topographic patterns for directing the formation of self-assembled domains at specified locations on substrates. The methods include generating mathematical models that operate on mathematical descriptions of the number and locations of cylindrical self-assembled domains in a mathematical description of a guiding pattern.Type: ApplicationFiled: May 16, 2012Publication date: March 24, 2016Applicant: INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Joy Cheng, Kafai Lai, Chi-Chun Liu, Jed W. Pitera, Charles T. Rettner
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Patent number: 9084735Abstract: Cationic, anionic, and/or zwitterionic bis-urea compounds self-assemble by non-covalent interactions in aqueous solution to form high aspect ratio nanofibers. The nanofibers reversibly bind drugs by non-covalent interactions, forming drug compositions for exhibiting sustained release of the drug.Type: GrantFiled: August 1, 2013Date of Patent: July 21, 2015Assignees: International Business Machines Corporation, Agency For Science, Technology And ResearchInventors: Daniel J. Coady, Richard A. Dipietro, Amanda C. Engler, James L. Hedrick, Shao Qiong Liu, Jed W. Pitera, Shrinivas Venkataraman, Yi Yan Yang
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Publication number: 20150037390Abstract: Cationic, anionic, and/or zwitterionic bis-urea compounds self-assemble by non-covalent interactions in aqueous solution to form high aspect ratio nanofibers. The nanofibers reversibly bind drugs by non-covalent interactions, forming drug compositions for exhibiting sustained release of the drug.Type: ApplicationFiled: August 1, 2013Publication date: February 5, 2015Applicants: AGENCY FOR SCIENCE, TECHNOLOGY AND RESEARCH, INTERNATIONAL BUSINESS MACHINES CORPORATIONInventors: Daniel J. Coady, Richard A. Dipietro, Amanda C. Engler, James L. Hedrick, Shao Qiong Liu, Hareem T. Maune, Alshakim Nelson, Jed W. Pitera, Shrinivas Venkataraman, Yi Yan Yang
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Patent number: 8656322Abstract: A design layout including shapes of target areas for forming semiconductor fins employing directed self-assembly can be decomposed into guiding patterns and cut patterns. The lengthwise edges of the shapes of target areas are adjusted. Widthwise edges of the adjusted shapes are extended outward to generate diffusion shapes. Guiding pattern shapes are then generated employing the diffusion shapes. Taper edges are adjusted based on process bias of a photoresist material to be subsequently employed. Optionally, a portion of a guiding pattern shape between diffusion shapes may be removed as a connection shape. The guiding pattern shapes can define at least one guiding pattern mask for lithographic pattern of guiding pattern shapes, and cut shapes can be derived from the diffusion shapes and the guiding pattern shapes. The guiding pattern shapes and the cut shapes may be adjusted to accommodate effects at device cell edges and at device macro edges.Type: GrantFiled: January 18, 2013Date of Patent: February 18, 2014Assignee: International Business Machines CorporationInventors: Daniel J. Dechene, Michael A. Guillorn, Kafai Lai, Jed W. Pitera, HsinYu Tsai