Patents by Inventor Jee-Eun Jung

Jee-Eun Jung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20230194975
    Abstract: An optical proximity correction system and an operating method are provided. Provided is an optical proximity correction system comprising, a plurality of patch blocks which include a plurality of patches including a segment information table, a plurality of slave devices which receive the segment information table from the plurality of patch blocks to generate a minimum patch table, and a master device which receives the minimum patch table from the plurality of slave devices, generates a segment average calculation table, and performs an optical proximity correction on the patches recorded in the segment average calculation table.
    Type: Application
    Filed: July 26, 2022
    Publication date: June 22, 2023
    Inventors: Hee-Jun LEE, Sang Wook KIM, Heung Suk OH, Jee Eun JUNG
  • Patent number: 9431245
    Abstract: A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is equal to or less than a resolution of a lithography process, the patterns are apportioned among a plurality of masks such that in each of the masks the space between adjacent ones of the patterns is greater than the resolution, and a dual pattern is added to one of the masks. A semiconductor pattern is formed on a substrate using the mask(s) and the mask to which the dual pattern has been added. Patterns having a pitch equal to or less than the resolution may be formed on the semiconductor device.
    Type: Grant
    Filed: May 23, 2014
    Date of Patent: August 30, 2016
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jee-Eun Jung, Kyoung-Yun Baek, Jeong-Hoon Lee
  • Publication number: 20150104887
    Abstract: A method of manufacturing a semiconductor device includes generating a mask layout of patterns in which the distance between adjacent ones of the patterns is equal to or less than a resolution of a lithography process, the patterns are apportioned among a plurality of masks such that in each of the masks the space between adjacent ones of the patterns is greater than the resolution, and a dual pattern is added to one of the masks. A semiconductor pattern is formed on a substrate using the mask(s) and the mask to which the dual pattern has been added. Patterns having a pitch equal to or less than the resolution may be formed on the semiconductor device.
    Type: Application
    Filed: May 23, 2014
    Publication date: April 16, 2015
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: JEE-EUN JUNG, KYOUNG-YUN BAEK, JEONG-HOON LEE
  • Patent number: 8689150
    Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.
    Type: Grant
    Filed: February 28, 2012
    Date of Patent: April 1, 2014
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Jee-eun Jung, Kyoung-yun Baek, Seong-woon Choi
  • Publication number: 20120220058
    Abstract: A method of fabricating a semiconductor device includes preparing a layout of the semiconductor device, obtaining contrast of an exposure image of the layout through a simulation under a condition of using a crosspole illumination system, separating the layout into a plurality of sub-layouts based on the contrast of the exposure image, forming a photomask having a mask pattern corresponding to the plurality of sub-layouts, and performing an exposure process using the photomask under an exposure condition of using a dipole illumination system.
    Type: Application
    Filed: February 28, 2012
    Publication date: August 30, 2012
    Inventors: Jee-eun JUNG, Kyoung-yun Baek, Seong-woon Choi
  • Patent number: 7745899
    Abstract: An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged in parallel, gate tab mask patterns formed on both sides of each gate line mask pattern, and joints formed between adjacent gate tab mask patterns, and that include a separation region. A relatively large gate tab mask pattern can be formed using the photomask. And a short channel effect at the boundary of the active region can be improved with the large gate tab mask pattern, so the characteristics and reliability of the semiconductor devices can be improved.
    Type: Grant
    Filed: August 1, 2007
    Date of Patent: June 29, 2010
    Assignee: Samsung Electronics Co., Ltd.
    Inventors: Ho-Jin Oh, Je-Min Park, Jee-Eun Jung
  • Publication number: 20080054354
    Abstract: A photo mask, a semiconductor integrated circuit, and a method of manufacturing the same are provided. The photo mask includes light transmitting rows and recess trenches, respectively, that include a short region in every other light transmitting row. In the semiconductor integrated circuit, the short region may include a dummy transistor so that short-circuiting bridges that may occur between adjacent recess trenches will not adversely affect the operations of the semiconductor integrated circuit.
    Type: Application
    Filed: September 4, 2007
    Publication date: March 6, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jin OH, Jee-Eun JUNG
  • Publication number: 20080044989
    Abstract: An embodiment of a photomask for forming gate lines and a method of manufacturing semiconductor devices using the photomask is disclosed. The photomask includes a photomask substrate, gate line mask patterns that define gate lines that cross at least one active region on a semiconductor substrate, and that are arranged in parallel, gate tab mask patterns formed on both sides of each gate line mask pattern, and joints formed between adjacent gate tab mask patterns, and that include a separation region. A relatively large gate tab mask pattern can be formed using the photomask. And a short channel effect at the boundary of the active region can be improved with the large gate tab mask pattern, so the characteristics and reliability of the semiconductor devices can be improved.
    Type: Application
    Filed: August 1, 2007
    Publication date: February 21, 2008
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Ho-Jin OH, Je-Min PARK, Jee-Eun JUNG