Abstract: A display substrate according to the embodiment includes: a base material having a long direction and a short direction, and including one surface and the other surface, and a first region and a second region; and a hole passing through the one surface and the other surface of the base material, wherein the first region is defined as a folding region in which the one surface is folded to face, the second region is defined as an unfolding region, the hole includes a first hole formed in the first region, and the first hole includes at least three first holes having different sizes in the long direction of the base material.

Abstract: An image processing device according to one embodiment comprises a processing unit which receives first Bayer data from an image sensor, receives gyro data from a gyro sensor, and generates, from the first Bayer data, by using the received gyro data, second Bayer data compensated for camera movement.

Abstract: Provided is a method for determining the wetting degree of a lithium ion battery cell using a low current test. The wetting degree determination method according to the present disclosure includes a) obtaining, as a reference charge profile, a charge profile recorded while charging a reference battery cell having undergone receiving an electrode assembly and an electrolyte solution in a case, assembling and pre-aging with a low current of 0.01 C-rate or less, b) measuring and recording a charge profile while charging another battery cell having undergone receiving an electrode assembly and an electrolyte solution in a case, assembling and pre-aging with a low current of 0.01 C-rate or less in the same way as the reference battery cell, and c) determining the wetting degree of another battery cell relative to the reference battery cell by comparative analysis of the reference charge profile and the measured charge profile.

Abstract: In an alloy metal plate according to an embodiment, diffraction intensity of a (111) plane of the alloy metal plate is defined as I (111), diffraction intensity of a (200) plane of the alloy metal plate is defined as I (200), diffraction intensity of a (220) plane of the alloy metal plate is defined as I (220), a diffraction intensity ratio of I (200) is defined by the following Equation 1, and a diffraction intensity ratio of I (220) is defined by the following Equation 2. At this time, the A is 0.5 to 0.6, the B is 0.3 to 0.5, and the value A may be larger than a value B. A = I ? ( 200 ) / { I ? ( 200 ) + I ? ( 220 ) + I ? ( 111 ) } [ Equation ? 1 ] The diffraction intensity ratio of I (220) is defined by the following Equation 2.

Abstract: A camera module includes a first driving part on a lower surface of an image sensor substrate, and a second driving part on a lower surface of the housing to face a lower surface of the first driving part. The first driving part includes a first driving part of a first group configured to move the image sensor substrate in a first direction with respect to the lens barrel, and a second driving part of a second group configured to move the image sensor substrate in a second direction intersecting the first direction with respect to the lens barrel. The second driving part includes a second driving part of a first group disposed overlapping the first driving part of the first group in a vertical direction, and a second driving part of a second group disposed overlapping the first driving part of the second group in the vertical direction.

Abstract: A battery module according to one embodiment of the present disclosure includes: a cell stack including one or more battery cells; a mono frame accommodating the cell stack therein; and a thermally conductive resin layer positioned between a lower portion of the cell stack and the mono frame. The battery module further includes a spring positioned between an upper portion of the cell stack and the mono frame.

Abstract: A nonvolatile memory device includes a first lower interlayer insulation layer and a second lower interlayer insulation layer that are sequentially stacked in a first direction; a lower metal layer disposed in the first lower interlayer insulation layer; and a plurality of lower bonding metals disposed in the first lower interlayer insulation layer and the second lower interlayer insulation layer and spaced apart from each other in a second direction that intersects the first direction. An uppermost surface in the first direction of the lower metal layer is lower than an uppermost surface in the first direction of the plurality of lower bonding metals, and the lower metal layer is placed between the plurality of lower bonding metals.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

Abstract: An induction heating apparatus according to one embodiment may confirm a feature of a container and determine an operation mode based on the feature of the container before performing an operation of heating the container. In one embodiment, the operation mode of the induction heating apparatus may be determined as any one of a frequency doubler mode, a half bridge mode, and a full bridge mode. In one embodiment, a power control mode of the induction heating apparatus may be determined based on an operation mode of the induction heating apparatus. In one embodiment, the power control mode of the induction heating apparatus may be determined as any one of an asymmetric pulse width modulation (APWM) mode and a phase shift mode.

Abstract: An audio-visual system may include a housing comprising an open upper end and a storage space, an audio-visual device installed inside the housing and exposable through the open upper end, and a lifting device configured to expose or store the audio-visual device inside the housing through the open upper end. The audio-visual device may include a display, a speaker, and a processor configured to control the audio-visual system to operate in a first mode for outputting media art content while the display is stored in the housing according to a first event, operate in a second mode for outputting audio content through the speaker while part of the display is exposed through the open upper end according to a second event, and operate in a third mode for outputting a visual content while the entire display is exposed through the open upper end according to a third event.

Abstract: A battery module according to one embodiment of the present disclosure includes a battery cell stack including a plurality of battery cells; a module frame surrounding the battery cell stack; a bus bar frame that covers a portion of the battery cell stack exposed from the module frame; and a bus bar mounted on the bus bar frame and connected to an electrode lead protruding from the battery cell stack, wherein a cooling flow path is formed in the bus bar.

Abstract: An apparatus and method are disclosed for detecting a bonding defect occurring during an ultrasonic wire bonding process between a battery cell and a busbar connected to each other by ultrasonic wire bonding. A bonding parameter collector, coupled to an ultrasonic wire bonding machine, may collect ultrasonic bonding parameters continuously during the ultrasonic wire bonding process, machine learning training may be performed by a convolutional neural network, and a bonding defect may be detected based thereon.

Abstract: A semiconductor memory device includes a lower stacked structure with lower metal lines on a substrate, an upper stacked structure with an upper metal line on the lower stacked structure, a vertical structure penetrating the upper and lower stacked structures and including a channel layer, a first cutting line through the upper and lower stacked structures, an upper supporter in a recess on the first cutting line, a second cutting line through the upper and lower stacked structures and spaced apart from the first cutting line, a sub-cutting line through the upper stacked structure while at least partially overlapping the vertical structure in the vertical direction, the sub-cutting line being between the first and second cutting lines, top surfaces of the upper supporter and sub-cutting line being coplanar, and a first interlayer insulating layer surrounding a sidewall of each of the upper supporter and the sub-cutting line.

Abstract: A semiconductor memory device includes a third insulating pattern and a first insulating pattern on a substrate, the third insulating pattern and the first insulating pattern being spaced apart from each other in a first direction that is perpendicular to the substrate such that a bottom surface of the third insulating pattern and a top surface of the first insulating pattern face each other, a gate electrode between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and including a first side extending between the bottom surface of the third insulating pattern and the top surface of the first insulating pattern, and a second insulating pattern that protrudes from the first side of the gate electrode by a second width in a second direction, the second direction being different from the first direction.

Abstract: An embodiment of a display device includes a substrate, a semiconductor layer, a first gate insulating layer, a gate electrode, a second gate insulating layer, a first storage electrode, a first interlayer insulating layer, a second interlayer insulating layer, a data line, and a driving voltage line. The semiconductor layer is disposed on the substrate. The first gate insulating layer is disposed on the semiconductor layer. The gate electrode is positioned on the first insulating layer. The second gate insulating layer is disposed on the gate electrode. The first storage electrode is positioned on the second gate insulating layer. The first interlayer insulating layer is disposed on the first storage electrode and has an opening surrounding the semiconductor layer, the gate electrode, and the first storage electrode. The second interlayer insulating layer is disposed on the first interlayer insulating layer and fills the opening.

Abstract: A semiconductor memory includes metallic lines on a substrate and including an uppermost metallic line, a semiconductor conduction line on the uppermost metallic line, a vertical structure penetrating the semiconductor conduction line and metallic lines, and including a vertical structure that includes an upper channel film, a first lower channel film, and an upper connection channel film connecting the upper channel film and the first lower channel film between a bottom of the semiconductor conduction line and a bottom of the uppermost metallic line, and a first cutting line through the metallic lines and the semiconductor conduction line, and including a first upper cutting line through the semiconductor conduction line, and a first lower cutting line through the plurality of metallic lines, a width of the first upper cutting line being greater than a width of an extension line of a sidewall of the first lower cutting line.

Abstract: Provided is a nonvolatile memory device. The nonvolatile memory device includes a conductive plate, a barrier conductive film extending along a surface of the conductive plate, a mold structure including a plurality of gate electrodes sequentially stacked on the barrier conductive film, a channel hole penetrating the mold structure to expose the barrier conductive film, an impurity pattern being in contact with the barrier conductive film, and formed in the channel hole, and a semiconductor pattern formed in the channel hole, extending from the impurity pattern along a side surface of the channel hole, and intersecting the plurality of gate electrodes.

Abstract: A display device includes a data conductive layer including a first power line, a passivation layer with a first opening exposing the first power line, a via layer with a second opening partially overlapping the first opening, a pixel electrode on the via layer, a connection electrode in the first and second openings, a pixel-defining film with an opening overlapping the second opening, a light-emitting layer on the pixel-defining film, the pixel electrode and the connection electrode, and a common electrode connected to the first power line. The data conductive layer includes a data base layer, a data main metal layer, and a data capping layer, the first power line includes a wire connection structure, in which the data main metal layer is recessed from sides of the data capping layer, and the common electrode is connected to the data main metal layer in the wire connection structure.

Abstract: A transistor array substrate includes a substrate, an active layer disposed on the substrate and including a channel region, a source region and a drain region, a gate insulating layer disposed on a part of the active layer, a gate electrode overlapping the channel region of the active layer and included in an electrode conductive layer which is disposed on the gate insulating layer, a source electrode included in the electrode conductive layer and in contact with a part of the source region of the active layer, and a drain electrode included in the electrode conductive layer and in contact with a part of the drain region of the active layer. The active layer includes an oxide semiconductor including crystals and is disposed as an island shape excluding a hole in a plan view.