Abstract: A semiconductor device includes a first semiconductor structure including circuit devices and first bonding pads; and a second semiconductor structure connected to the first semiconductor structure, the second semiconductor structure including a base layer; a first memory cell structure including first gate electrodes and first channels penetrating through the first gate electrodes; a second memory cell structure including second gate electrodes and second channels penetrating through the second gate electrodes; bit lines between the first and the second memory cell structures, and electrically connected to the first and second channels in common; first and second conductive layers on the second surface of the base layer; a pad insulating layer having an opening exposing a portion of the second conductive layer; and second bonding pads disposed to correspond to the first bonding pads in a lower portion of the second memory cell structure.

Abstract: A three-dimensional semiconductor device includes a first substrate, a second substrate on the first substrate, the second substrate including pattern portions and a plate portion covering the pattern portions, the plate portion having a width greater than a width of each of the pattern portions and being connected to the pattern portions, a lower structure between the first substrate and the second substrate, horizontal conductive patterns on the second substrate, the horizontal conductive patterns being stacked while being spaced apart from each other in a direction perpendicular to an upper surface of the second substrate, and a vertical structure on the second substrate and having a side surface opposing the horizontal conductive patterns.

Abstract: A scan driver has a plurality of stages configured to supply a scan signal to scan lines. The plurality of stages include a stage coupled to a scan line of the scan lines. The stage includes a first transistor including a gate electrode, a drain electrode and a source electrode and is configured to output the scan signal to the scan line; a second transistor provided on a side of the first transistor and connected to the drain electrode; a third transistor provided on the side of the first transistor and connected to the source electrode; a capacitor provided between the scan line and the first transistor; a first dummy transistor provided between the first transistor and the capacitor and connected to the capacitor; and a second dummy transistor provided between the first transistor and the second transistor and connected to both the first transistor and the second transistor.

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

Abstract: A liquid crystal display device includes a display area, a peripheral area, and a boundary area between the display area and the peripheral area and further includes: a first substrate; a switching element disposed on the first substrate in the display area; a pad disposed on the first substrate in the peripheral area and electrically connected with the switching element; a protective film disposed on the first substrate in the display area, the peripheral area, and the boundary area, and covering the switching element and the pad; a color filter disposed on the protective film in the display area; and a planarization film covering the color filter and contacting the protective film in the boundary area and the peripheral area. The planarization film is provided with a first opening overlapping the pad and at least one second opening formed in the boundary area.

Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.

Abstract: A secondary battery and a method of manufacturing the same are disclosed. In one aspect, the method includes preparing an electrode assembly comprising a positive electrode plate, a negative electrode plate, and a separator interposed therebetween. The method also includes freezing the electrode assembly after the electrode assembly is filled with an electrolyte solution, dipping the frozen electrode assembly in a liquid polymer material, retrieving the dipped electrode assembly from the liquid polymer material, and curing an external surface of the electrode assembly.

Abstract: A scan driver has a plurality of stages configured to supply a scan signal to scan lines. The plurality of stages include a stage coupled to a scan line of the scan lines. The stage includes a first transistor including a gate electrode, a drain electrode and a source electrode and is configured to output the scan signal to the scan line; a second transistor provided on a side of the first transistor and connected to the drain electrode; a third transistor provided on the side of the first transistor and connected to the source electrode; a capacitor provided between the scan line and the first transistor; a first dummy transistor provided between the first transistor and the capacitor and connected to the capacitor; and a second dummy transistor provided between the first transistor and the second transistor and connected to both the first transistor and the second transistor.

Abstract: A vertical non-volatile memory device includes a lower insulating layer on a substrate, a multilayer structure including gate electrodes and interlayer insulating layers alternately stacked on the lower insulating layer, a gate dielectric layer and a channel structure, and has an opening extending through the multilayer structure and exposing the lower insulating layer. The opening includes a first open portion extending through at least one layer of the multilayer structure at a first width, and a second open portion extending through the multilayer structure at a second width less than the first width. The gate dielectric layer lines the opening, and the channel structure is disposed on the gate dielectric layer and is electrically connected to the substrate.

Abstract: A liquid crystal display device includes a display area, a peripheral area, and a boundary area between the display area and the peripheral area and further includes: a first substrate; a switching element disposed on the first substrate in the display area; a pad disposed on the first substrate in the peripheral area and electrically connected with the switching element; a protective film disposed on the first substrate in the display area, the peripheral area, and the boundary area, and covering the switching element and the pad; a color filter disposed on the protective film in the display area; and a planarization film covering the color filter and contacting the protective film in the boundary area and the peripheral area. The planarization film is provided with a first opening overlapping the pad and at least one second opening formed in the boundary area.

Abstract: A method of fabricating a memory device includes forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes a pad portion and a line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as a mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. A lower mask pattern including at least one line mask, bridge mask, and pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.

Abstract: Vertical memory devices and methods of forming the same are provided. The devices may include a gate line structure including gate lines that are stacked in a first direction and extend in a second direction. The device may also include a first step pattern structure including extended gate lines extending from the gate lines and including first step layers and a second step pattern structure contacting the first step pattern structure, including the extended gate lines and including second step layers. An n-th extended gate line (n is an even number) may be disposed at an upper portion of each of the first step layers, and an (n?1)-th extended gate line may be disposed at an upper portion of each of the second step layers. Each of exposed portions of the (n?1)-th extended gate lines serves as a pad region, and the pad regions have different areas.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that includes a first main line having a first width and a first subline having a second width, and a second line pattern that includes a second main line having the first width and a second subline having a third width. The first line pattern may include a first width changer whose width increases from the first width to the second width. The second line pattern may include a second width changer whose width increases from the first width to the third width.

Abstract: A display device includes a first substrate including a display area and a peripheral area disposed in a periphery of the display area. A gate line is disposed in the display area. A data line is insulated from the gate line and intersects the gate line. The data line includes a first portion and a second portion. The first portion is disposed in the display area, and the second portion is connected to the first portion and is disposed in the peripheral area. A thin-film transistor (TFT) is disposed in the display area of the first substrate and is connected to the gate and data lines. A first insulating pattern is disposed on the TFT. A second insulating pattern is disposed in the peripheral area and covers a part of the second portion of the data line. The second insulating pattern includes a same material as the first insulating pattern.

Abstract: A display device in a display panel; a backlight unit configured to provide light to the display panel, the display pan& being arranged at a side of a first surface of the backlight unit; and a first light adjustment unit configured to be arranged at a side of a second surface of the backlight unit opposite to the first surface of the backlight unit, the first light adjustment unit including a plurality of reflection portions, reflection portions of the plurality of reflection portions being rotatable so as to be switchable between a light transmission mode and a light reflection mode.

Abstract: Semiconductor devices and methods of manufacturing the semiconductor devices are provided. The semiconductor devices may include a first line pattern that includes a first main line having a first width and a first subline having a second width, and a second line pattern that includes a second main line having the first width and a second subline having a third width. The first line pattern may include a first width changer whose width increases from the first width to the second width. The second line pattern may include a second width changer whose width increases from the first width to the third width.

Abstract: A secondary battery is disclosed. In one aspect, the battery includes an electrode assembly including i) a positive electrode plate on which a positive active material is formed, ii) a negative electrode plate on which a negative active material is formed, and iii) a separator separating the positive and negative electrode plates. The battery also includes a can accommodating the electrode assembly, wherein the can has an inner surface facing the electrode assembly, an inner active material layer formed on the inner surface of the can and a securing layer covering the inner active material layer.

Abstract: A semiconductor device includes first, second, and third conductive lines, each with a respective line portion formed over a substrate and extending in a first direction and with a respective branch portion extending from an end of the respective line portion in a direction different from the first direction. The branch portion of a middle conductive line is disposed between and shorter than the respective branch portions of the outer conductive lines such that contact pads may be formed integral with such branch portions of the conductive lines.

Abstract: A method of fabricating a flash memory device includes sequentially forming an etching object layer and a lower sacrificial layer on a substrate, and forming an upper sacrificial pattern structure on the lower sacrificial layer. The upper sacrificial pattern structure includes an upper sacrificial pad portion and an upper sacrificial line portion on the lower sacrificial layer. An upper spacer is formed by covering a side wall of the upper sacrificial pattern structure. A lower sacrificial pattern structure including a lower sacrificial pad portion and a lower sacrificial line portion is formed by etching the lower sacrificial layer, by using the upper sacrificial pad portion and the upper spacer as an etch mask. A lower spacer layer is formed by covering the lower sacrificial pattern structure. Finally, a lower mask pattern including at least one line mask, at least one bridge mask, and at least one pad mask, is formed by etching the lower spacer layer and the lower sacrificial pattern structure.