Patents by Inventor Jee-Hwan Song
Jee-Hwan Song has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20240137408Abstract: There are provided a method and a system for selecting an optimal synchronization broker for each workload. A system for selecting an optimal synchronization broker for each workload according to an embodiment includes: a storage unit including a database that contains specialist recommendation information including information on a correct protocol that is recommended by a specialist with respect to a service specification and data transmission requirements; and a processor configured to determine an optimal in-bound protocol and an optimal out-bound protocol according to the data transmission requirements through a decision tree model that is trained by using the specialist recommendation information as training data.Type: ApplicationFiled: October 16, 2023Publication date: April 25, 2024Applicant: Korea Electronics Technology InstituteInventors: Won Gi CHOI, Sang Shin LEE, Min Hwan SONG, Jee Hyeong KIM
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Publication number: 20240134690Abstract: There are provided a system and a method for setting a synchronization agent. A system for setting an optimal synchronization agent according to a workload according to an embodiment includes: a data integration device configured to integrate and store data which is collected through a collection agent; an agent management server configured to manage the collection agent that periodically polls data from a data source and transmits the data to the data integration device; and an agent setting automation device configured to set an optimal agent set value related to collection and transmission of data of the collection agent.Type: ApplicationFiled: October 16, 2023Publication date: April 25, 2024Applicant: Korea Electronics Technology InstituteInventors: Won Gi CHOI, Sang Shin LEE, Min Hwan SONG, Jee Hyeong KIM
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Patent number: 8423329Abstract: Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor.Type: GrantFiled: January 21, 2010Date of Patent: April 16, 2013Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, YonseiInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang
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Patent number: 8161430Abstract: Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.Type: GrantFiled: April 22, 2008Date of Patent: April 17, 2012Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon
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Publication number: 20110178768Abstract: Systems and methods of resistance-based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance-based memory circuit includes determining a range of sizes for a clamp transistor and selecting a set of clamp transistors having sizes within the determined range of sizes. For each clamp transistor in the set of clamp transistors, a simulation may be executed to generate a first contour graph representing current values over a range of statistical values. The first contour graph may be used to identify a read disturbance area and a design range of the gate voltage of the clamp transistor and a load of the clamp transistor. The method may execute a simulation to generate a second contour graph representing sense margin over a range of statistical values of the gate voltage of the clamp transistor and the load of the clamp transistor.Type: ApplicationFiled: January 21, 2010Publication date: July 21, 2011Applicants: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UniversityInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang
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Patent number: 7889585Abstract: A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.Type: GrantFiled: December 18, 2008Date of Patent: February 15, 2011Assignees: QUALCOMM Incorporated, Industry-Academic Cooperation Foundation, Yonsei UInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon, Mehdi Hamidi Sani
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Patent number: 7813166Abstract: Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.Type: GrantFiled: June 30, 2008Date of Patent: October 12, 2010Assignee: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon
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Publication number: 20100157654Abstract: A resistance based memory circuit is disclosed. The circuit includes a first transistor load of a data cell and a bit line adapted to detect a first logic state. The bit line is coupled to the first transistor load and coupled to a data cell having a magnetic tunnel junction (MTJ) structure. The bit line is adapted to detect data having a logic one value when the bit line has a first voltage value, and to detect data having a logic zero value when the bit line has a second voltage value. The circuit further includes a second transistor load of a reference cell. The second transistor load is coupled to the first transistor load, and the second transistor load has an associated reference voltage value. A characteristic of the first transistor load, such as transistor width, is adjustable to modify the first voltage value and the second voltage value without substantially changing the reference voltage value.Type: ApplicationFiled: December 18, 2008Publication date: June 24, 2010Applicant: QUALCOMM IncorporatedInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon, Mehdi Hamidi Sani
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Publication number: 20090323405Abstract: Systems and methods of controlled value reference signals of resistance based memory circuits are disclosed. In a particular embodiment, a circuit device is disclosed that includes a first input configured to receive a reference control signal. The circuit device also includes an output responsive to the first input to selectively provide a controlled value reference voltage to a sense amplifier coupled to a resistance based memory cell.Type: ApplicationFiled: June 30, 2008Publication date: December 31, 2009Applicant: QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Ji-Su Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon
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Publication number: 20090265678Abstract: Systems and methods of resistance based memory circuit parameter adjustment are disclosed. In a particular embodiment, a method of determining a set of parameters of a resistance based memory circuit includes selecting a first parameter based on a first predetermined design constraint of the resistance based memory circuit and selecting a second parameter based on a second predetermined design constraint of the resistance based memory circuit. The method further includes performing an iterative methodology to adjust at least one circuit parameter of a sense amplifier portion of the resistance based memory circuit by selectively assigning and adjusting a physical property of the at least one circuit parameter to achieve a desired sense amplifier margin value without changing the first parameter or the second parameter.Type: ApplicationFiled: April 22, 2008Publication date: October 22, 2009Applicants: QUALCOMM INCORPORATEDInventors: Seong-Ook Jung, Jisu Kim, Jee-Hwan Song, Seung H. Kang, Sei Seung Yoon