Patents by Inventor Jeekyoung Park
Jeekyoung Park has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).
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Publication number: 20250053522Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: ApplicationFiled: August 13, 2024Publication date: February 13, 2025Inventors: Jordan HORWICH, Jerry ALSTON, Chih-Cheh CHEN, Patrick LEE, Scott MILTON, Jeekyoung PARK
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Patent number: 12061562Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: GrantFiled: June 1, 2021Date of Patent: August 13, 2024Assignee: Netlist, Inc.Inventors: Jordan Horwich, Jerry Alston, Chih-Cheh Chen, Patrick Lee, Scott Milton, Jeekyoung Park
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Patent number: 12026397Abstract: A memory module according to some embodiments is operable in a computer system including a memory controller coupled to a memory channel. The memory module comprises a volatile memory subsystem, non-volatile (NV) memory subsystem and a module controller coupled to the volatile memory subsystem and the NV memory subsystem. The volatile memory subsystem includes dynamic random access memory (DRAM) devices and is configurable to communicate with the memory controller via the memory channel during memory read or write operations. The module controller is configured to output data strobe signals to accompany data from the volatile memory subsystem during a memory read operation and to output to accompany data strobes output by data buffers in response to data strobe signals from the memory controller during a system-initiated operation to transfer data from the NV memory subsystem to the volatile memory subsystem.Type: GrantFiled: November 29, 2022Date of Patent: July 2, 2024Assignee: Netlist, Inc.Inventors: Jeekyoung Park, Jordan Horwich
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Publication number: 20230280937Abstract: A memory module according to some embodiments is operable in a computer system including a memory controller coupled to a memory channel. The memory module comprises a volatile memory subsystem, non-volatile (NV) memory subsystem and a module controller coupled to the volatile memory subsystem and the NV memory subsystem. The volatile memory subsystem includes dynamic random access memory (DRAM) devices and is configurable to communicate with the memory controller via the memory channel during memory read or write operations. The module controller is configured to output first strobe signals to accompany first data signals from the volatile memory subsystem during a memory read operation and to output second strobe signals together with second data signals carrying data from the non-volatile memory subsystem during a system-initiated NV read operation.Type: ApplicationFiled: November 29, 2022Publication date: September 7, 2023Inventors: Jeekyoung Park, Jordan HORWICH
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Publication number: 20230214326Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: ApplicationFiled: June 1, 2021Publication date: July 6, 2023Inventors: Jordan HORWICH, Jerry ALSTON, Chih-Cheh CHEN, Patrick LEE, Scott MILTON, Jeekyoung PARK
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Patent number: 11513725Abstract: A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.Type: GrantFiled: September 16, 2020Date of Patent: November 29, 2022Assignee: Netlist, Inc.Inventors: Jeekyoung Park, Jordan Horwich
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Patent number: 11500797Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: GrantFiled: June 1, 2021Date of Patent: November 15, 2022Assignee: Netlist, Inc.Inventors: Jordan Horwich, Jerry Alston, Chih-Cheh Chen, Patrick Lee, Scott Milton, Jeekyoung Park
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Publication number: 20210374080Abstract: A memory expansion device operable with a host computer system (host) comprises a non-volatile memory (NVM) subsystem, cache memory, and control logic configurable to receive a submission from the host including a read command and specifying a payload in the NVM subsystem and demand data in the payload. The control logic is configured to request ownership of a set of cache lines corresponding to the payload, to indicate completion of the submission after acquiring ownership of the cache lines, and to load the payload to the cache memory. The set of cache lines correspond to a set of cache lines in a coherent destination memory space accessible by the host. The control logic is further configured to, after indicating completion of the submission and in response to a request from the host to read demand data in the payload, return the demand data after determining that the demand data is in the cache memory.Type: ApplicationFiled: June 1, 2021Publication date: December 2, 2021Inventors: Jordan HORWICH, Jerry ALSTON, Chih-Cheh CHEN, Patrick LEE, Scott MILTON, Jeekyoung PARK
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Publication number: 20210081138Abstract: A memory module according to some embodiments is operable in a computer system, and comprises a volatile memory subsystem and a module controller coupled to the volatile memory subsystem. The volatile memory subsystem is configurable to be coupled to a memory channel including a data bus, and includes dynamic random access memory (DRAM) devices. The memory module allows independent control of strobe paths and data paths between the DRAM devices and the data bus, and is configurable to perform a memory write operation during which write data is provided to the volatile memory subsystem together with write strobes transmitted via first strobe paths between the DRAM devices and the data bus, and a memory read operation during which read data from the volatile memory subsystem is output onto the data bus together with read strobes transmitted via second strobe paths between the module controller and the data bus.Type: ApplicationFiled: September 16, 2020Publication date: March 18, 2021Inventors: Jeekyoung Park, Jordan HORWICH
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Patent number: 7515706Abstract: A headset with retractable cord for portable devices with automatic switching capability system, comprising an electronic device, a headset, a cord extending between the electronic device and the headset, and a retracting assembly for retracting the cord into a coil during periods of non-use. Optionally, the system includes a retraction detection assembly for determining a condition of retraction of the cord with respect to the electronic device.Type: GrantFiled: November 22, 2005Date of Patent: April 7, 2009Assignee: Gateway Inc.Inventor: Jeekyoung Park
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Publication number: 20070121985Abstract: A headset with retractable cord for portable devices with automatic switching capability system, comprising an electronic device, a headset, a cord extending between the electronic device and the headset, and a retracting assembly for retracting the cord into a coil during periods of non-use.Type: ApplicationFiled: November 22, 2005Publication date: May 31, 2007Inventor: Jeekyoung Park
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Patent number: 7209113Abstract: A hand-held computing system includes a housing with an elongated opening for receiving a nonelectronic input device. The elongated opening has an inside surface. At least two electrical contacts are positioned on the inside surface of the elongated opening. A connector includes at least two electrical contacts for electrically contacting the at least two electrical contacts on the inside surface of the elongated opening. A cable or other electrical connector places a peripheral computing device, battery or keyboard, in communication with the microprocessor within the housing of the personal data assistant.Type: GrantFiled: May 9, 2002Date of Patent: April 24, 2007Assignee: Gateway Inc.Inventor: Jeekyoung Park
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Publication number: 20030210223Abstract: A hand-held computing system includes a housing with an elongated opening for receiving a nonelectronic input device. The elongated opening has an inside surface. At least two electrical contacts are positioned on the inside surface of the elongated opening. A connector includes at least two electrical contacts for electrically contacting the at least two electrical contacts on the inside surface of the elongated opening. A cable or other electrical connector places a peripheral computing device, battery or keyboard, in communication with the microprocessor within the housing of the personal data assistant.Type: ApplicationFiled: May 9, 2002Publication date: November 13, 2003Applicant: Gateway, Inc.Inventor: Jeekyoung Park
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Publication number: 20020185259Abstract: An angle-mounted fan sink for an electronic device, such as the processor of a computer system, or the like includes a heat sink coupled to a surface of the electronic device for conducting heat away from the electronic device. A fan assembly is mounted in an oblique orientation to the base of the heat sink. The fan assembly circulates a cooling medium such as air over the heat sink at an angle that is generally oblique to the surface of the electronic device for dissipating heat from the heat sink.Type: ApplicationFiled: May 7, 2002Publication date: December 12, 2002Applicant: Gateway, Inc.Inventor: Jeekyoung Park