Patents by Inventor Jee Mok

Jee Mok has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Publication number: 20060144618
    Abstract: A fill plated structure of an inner via hole, which includes an electroless plated layer formed on a copper clad laminate having an inner via hole formed therethrough, a first copper electroplated layer formed on the electroless plated layer on the copper clad laminate and formed on an inner wall of the via hole to form an belly portion having a belly shape, and a second copper electroplated layer formed on the first copper electroplated layer of a surface of the copper clad laminate and formed on upper and lower portions of the first copper electroplated layer of the inner wall of the via hole to fill the via hole; and a method of manufacturing the same.
    Type: Application
    Filed: May 24, 2005
    Publication date: July 6, 2006
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Chang Song, Tae Kim, Kyung Kim, Woo Lee, Jee Mok
  • Publication number: 20060102383
    Abstract: Disclosed is a method of fabricating a high density PCB. Electric properties of a high frequency package product are reduced due to an increased length of a circuit even though the increased length of the circuit is necessary to maintain physical strength in the course of fabricating the PCB. Accordingly, a core insulating layer is removed, thereby providing a method of fabricating a slim PCB having a short wiring length.
    Type: Application
    Filed: February 10, 2005
    Publication date: May 18, 2006
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Hye Cha, Byung Sun, Tae Kim, Jee Mok
  • Publication number: 20060046485
    Abstract: Disclosed herein is a method of manufacturing a package substrate with a fine circuit pattern using anodic oxidation. By anodizing a metal core which is opened through a masking process, oxidation layers are formed in open areas of the metal core to insulate portions of circuit pattern from each other. Further, by electroplating portions provided between the oxidation layers with copper or filling conductive paste between the oxidation layers using a screen, a package substrate having a fine circuit pattern is achieved.
    Type: Application
    Filed: December 13, 2004
    Publication date: March 2, 2006
    Applicant: Samsung Electro-Mechanics Co., Ltd.
    Inventors: Duck Maeng, Byung Sun, Tae Kim, Jee Mok, Jong Bae, Yoong Oh, Chang-Kyu Song, Suk-Hyeon Cho
  • Patent number: 5928994
    Abstract: Control of weeds in a rice crop is obtained by applying to the crop, the weeds, or the locus of either, a herbicidal composition containing molinate and oxyfluorfen in a weight ratio of from about 500:1 to about 30:1.
    Type: Grant
    Filed: September 2, 1998
    Date of Patent: July 27, 1999
    Assignee: Zeneca Limited
    Inventors: Richard L. Franz, Jee Mok Fua, Khosro Khodayari