Patents by Inventor Jee-Won Chung

Jee-Won Chung has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Method of manufacturing a molded flip chip package to facilitate electrical testing
    Patent number: 11784100
    Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.
    Type: Grant
    Filed: October 15, 2021
    Date of Patent: October 10, 2023
    Assignee: SK hynix Inc.
    Inventors: Jee Won Chung, Dong Jin Kim, Byeung Ho Kim, Chang Hyun Kim
  • METHOD OF MANUFACTURING A FLIP CHIP PACKAGE AND AN APPARATUS FOR TESTING FLIP CHIPS
    Publication number: 20220037214
    Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.
    Type: Application
    Filed: October 15, 2021
    Publication date: February 3, 2022
    Applicant: SK hynix Inc.
    Inventors: Jee Won CHUNG, Dong Jin KIM, Byeung Ho KIM, Chang Hyun KIM
  • Method of manufacturing a flip chip package and an apparatus for testing flip chips
    Patent number: 11177184
    Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.
    Type: Grant
    Filed: October 30, 2019
    Date of Patent: November 16, 2021
    Assignee: SK hynix Inc.
    Inventors: Jee Won Chung, Dong Jin Kim, Byeung Ho Kim, Chang Hyun Kim
  • METHOD OF MANUFACTURING A FLIP CHIP PACKAGE AND AN APPARATUS FOR TESTING FLIP CHIPS
    Publication number: 20200357705
    Abstract: A method of manufacturing a flip chip package includes forming a plurality of semiconductor chips and bonding the semiconductor chips to a package substrate. The method further includes electrically testing the plurality of semiconductor chips on the package substrate, molding the tested semiconductor chips, and singulating the molded chips. Electrically testing the semiconductor chips includes covering the semiconductor chips with a protection member.
    Type: Application
    Filed: October 30, 2019
    Publication date: November 12, 2020
    Applicant: SK hynix Inc.
    Inventors: Jee Won CHUNG, Dong Jin KIM, Byeung Ho KIM, Chang Hyun KIM
  • Magnetoresistance device and method of fabrication using titanium nitride as capping layer
    Publication number: 20060132986
    Abstract: A magnetoresistance device using TiN as a capping layer and a method of fabricating the same. The fabrication of the magnetoresistance device may be simpler and the magentoresistance device may be more stable and/or more reliable.
    Type: Application
    Filed: December 16, 2005
    Publication date: June 22, 2006
    Inventors: Soon-Won Hwang, Tae-Wan Kim, Seok-Jae Chung, Yong-Hwan Yoo, Jee-Won Chung