Abstract: An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a first internal voltage generation circuit configured to provide a reference internal voltage to either an internal voltage control circuit or a node at which an output internal voltage is generated. The internal voltage generation circuit may include a second internal voltage generation circuit configured to change a level of the output internal voltage. The internal voltage generation circuit may include an internal voltage control circuit configured to compare the reference internal voltage with the output internal voltage and control the first and second internal voltage generation circuits to change the level of the output internal voltage according to a comparison.

Abstract: A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.

Abstract: A semiconductor memory device includes a reference voltage generation block suitable for selecting and outputting one of a plurality of reference voltages in response to a voltage division enable signal, as an input reference voltage, in response to a selection enable signal; and a control signal generation block suitable for generating the voltage division enable signal and the selection enable signal in response to a reference voltage information.

Abstract: A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. The sub-load circuit may compensate mismatch between rising timing and falling timing of the first output signal based on the first input signal.

Abstract: A buffer circuit may include an amplification circuit, a main load circuit, and a sub-load circuit. The amplification circuit and the main load circuit may generate first and second output signals by amplifying first and second input signals. The sub-load circuit may compensate mismatch between rising timing and falling timing of the first output signal based on the first input signal.

Abstract: An internal voltage generation circuit may be provided. The internal voltage generation circuit may include a first internal voltage generation circuit configured to provide a reference internal voltage to either an internal voltage control circuit or a node at which an output internal voltage is generated. The internal voltage generation circuit may include a second internal voltage generation circuit configured to change a level of the output internal voltage. The internal voltage generation circuit may include an internal voltage control circuit configured to compare the reference internal voltage with the output internal voltage and control the first and second internal voltage generation circuits to change the level of the output internal voltage according to a comparison.