Patents by Inventor Jeehwan Heo

Jeehwan Heo has filed for patents to protect the following inventions. This listing includes patent applications that are pending as well as patents that have already been granted by the United States Patent and Trademark Office (USPTO).

  • Patent number: 11765880
    Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.
    Type: Grant
    Filed: April 30, 2021
    Date of Patent: September 19, 2023
    Assignee: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanghee Lee, Seokhan Park, Sungchang Park, Boun Yoon, Ilyoung Yoon, Youngsuk Lee, Junseop Lee, Seungho Han, Jaeyong Han, Jeehwan Heo
  • Publication number: 20230005935
    Abstract: A semiconductor device may include a substrate, a patterned structure, a filling pattern, and a conductive spacer. The substrate may include a semiconductor chip region and an overlay region. The patterned structure may include bit line structures spaced by a first distance on the semiconductor region, define a first trench and a second trench on first and second regions of the overlay region, and include key structures on the second region and spaced apart by the second trench. The filling pattern may fill lower portions of the first and second trenches on the first and second regions. The first region may be an edge portion of the overlay region. The second region may be a central portion of the overlay region. The conductive spacer may contact an upper surface of the filling pattern and may be on an upper sidewall of each of the first and second trenches.
    Type: Application
    Filed: April 5, 2022
    Publication date: January 5, 2023
    Applicant: Samsung Electronics Co., Ltd.
    Inventors: Yanghee LEE, Jonghyuk PARK, Ilyoung YOON, Boun YOON, Jeehwan HEO
  • Publication number: 20220115379
    Abstract: A method of manufacturing a semiconductor device includes: forming a lower structure that includes a substrate and conductive lines on the substrate, within a chip region and an edge region of the lower structure; forming data storage structures on the chip region of the lower structure; forming dummy structures on the edge region of the lower structure; forming an interlayer insulating layer covering the data storage structures and the dummy structures on the lower structure, the interlayer insulating layer including high step portions and low step portions, an upper end of the low step portions being lower than an upper end of the high step portions; and planarizing the interlayer insulating layer.
    Type: Application
    Filed: April 30, 2021
    Publication date: April 14, 2022
    Applicant: SAMSUNG ELECTRONICS CO., LTD.
    Inventors: Yanghee Lee, Seokhan Park, Sungchang Park, Boun Yoon, Ilyoung Yoon, Youngsuk Lee, Junseop Lee, Seungho Han, Jaeyong Han, Jeehwan Heo